AD9546 1pps

Hi,

I am very sorry for getting back to you so late. Your issue was lost in my emails.

I recommend applying the 1Hz, 1.8V CMOS clock at REFBB input of the evaluation board because that input is already dc coupled.

Then I recommend you apply a 10MHz OCXO, ac coupled at REFA input to stabilize the system clock wonder created by the 52 MHz crystal resonator.

Please take a look at the attached stp file.  Please take out the txt extension before using it.

AD9546_setup_1Hz_20230621.json.txt

Petre

Hi, 

Thanks for your reply.

Hi Petre,

We want to make synchronization unit/block in our Project. The synchronizer signal will be obtanied from a GPS/GNSS. The figure below shows a pseudo-schematic of the block like a summary:

(Input/In/input signal stands for synchronizer signal at REFBB pin of AD9546)

There are three cases :

Case-1: When the unit/block is powered up, there is no input signal available.

1. AD9546 generates an 1Hz(1pps) output with minimum jitter in pulse?
2. Which mode (Buildout/FreeRun/Holdover etc.) AD9546 run in?

Case-2: Then, the input signal is available (Time pulse with jitter of ±30ns).        

1. How much time is required to synchronize to the input signal (1pps from GPS)?
2. What is the maximum phase difference between in and output? (We must achieve a phase difference between the input signal and output less than 5ns.)
3. Can we achieve 0ns phase difference between input signal (reference signal at REFBB) and output of AD9546?

Case-3: Lastly, the input signal is faulted (not available, invalid,… etc.) anymore

1. AD9546 switches to Holdover or Freerun?
2. What is the difference between Holdover and Freerun mode?
3. AD9546 continues to generate a 1Hz signal at output after switching to the holdover mode? How much time is required to switch to the holdover mode?
4. There can occur any jitter/frequency phase discontinuity at the output of AD9546 when switching to the holdover mode?
5. How long it generates an output stably in holdover mode?
6. AD9546 is switched to the Holdover mode automatically or manually forced?

I know there are alot of questions but so important for us (especially, Case-1 to Case-2; Case-2 to Case-3 then Case-3 to Case-2)

Note: in AD9546 Evaluation Software v.1.3.0.0, Channel-0->DIST SETTINGS->Distribution Sync. what is the role of this command?

Thansk for your interest.

Hi,

my understanding is that you also contacted me through another channel and we have a call setup in a couple of days.

So please use only one single communication channel. I suggest to stop posting on EZ and use the other channel.

A lot of answers to your questions may be found in the data sheet.

Case-1: When the unit/block is powered up, there is no input signal available.

1. AD9546 generates an 1Hz(1pps) output with minimum jitter in pulse?

Petre: Yes because the APLL is calibrated and the DPLL generates the freerun tuning word to it. The phase noise over 50 mHz DPLL loop bandwidth will be the one you can see in the Typical Performance plots. See figure 11, page 43, in the data sheet.

1. Which mode (Buildout/FreeRun/Holdover etc.) AD9546 run in?

Petre: it will be be freerun because I suppose "no input signal available" means that the reference clock to the DPLL is considered invalid by the AD9546.

Case-2: Then, the input signal is available (Time pulse with jitter of ±30ns).        

1. How much time is required to synchronize to the input signal (1pps from GPS)?

Petre: It depends on a lot of factors. Let's say the DPLL is set in internal zero delay mode. The most important factor in my experience is the phase slew rate limit , which by default is around 100us/s. This means the 1Hz output is allowed to move towards the 1Hz reference at 100us every second. Worst case, the initial phase offset is 500ms. Divide 500ms by 100us and you can see how many seconds take to bring the output in phase to the reference in this worst case. 

If your application allows, the phase slew rate limit could be set to the max value, 2^32-1, which is approximately 4ms/s. This leaves the DPLL to function most of the time at its natural speed.

After power up, you can use the Reference Sync feature (page 112). This speeds up considerably the locking speed. But I recommend starting to use this feature after you got some experience locking the DPLL onto a 1Hz reference clock. Again, this functions only once, after power up.

1. What is the maximum phase difference between in and output? (We must achieve a phase difference between the input signal and output less than 5ns.)

Petre: I suppose the the question is how much is the max phase offset after DPLL becomes locked. This is determined by the phase lock threshold and frequency lock threshold. By default, they are 700ps at DPD level. See the DPLL Propagation delay specification at page 23 to see the actual numbers that can be achieved.

1. Can we achieve 0ns phase difference between input signal (reference signal at REFBB) and output of AD9546?

Petre: Yes, you can compensate the typical propagation delays mentioned above in the  DPLL. See section DPLL phase offset control section at page 132.

Case-3: Lastly, the input signal is faulted (not available, invalid,… etc.) anymore

1. AD9546 switches to Holdover or Freerun?

Petre: it switches to holdover. There are associated settings that dictate the tuning word value at holdover. See tuning word history section at page 135.

1. What is the difference between Holdover and Freerun mode?

Petre: You saw already my answers to your related questions

1. AD9546 continues to generate a 1Hz signal at output after switching to the holdover mode? How much time is required to switch to the holdover mode?

Petre: The 1Hz output is generated continuously when the AD9546 switches from an active profile state to the holdover state. The switching time is determined by the time it takes the AD9546 to understand the reference clock is invalid. Once it determined this, the switch is instantaneous. Again, the output is not affected by the switch.

1. There can occur any jitter/frequency phase discontinuity at the output of AD9546 when switching to the holdover mode?

Petre: No

1. How long it generates an output stably in holdover mode?

Petre: as long as the system clock stability is compensated using the auxiliary DPLL and the auxiliary DPLL reference clock is provided by an OCXO.

1. AD9546 is switched to the Holdover mode automatically or manually forced?

Petre: it depends on how you set it up. By default, it switches automatically. See page 147.

Note: in AD9546 Evaluation Software v.1.3.0.0, Channel-0->DIST SETTINGS->Distribution Sync. what is the role of this command?

Petre: without the sync command, the AD9546 cannot generate outputs. This command may be generated automatically or manually. See page 111.

Petre