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AD9517-3 Phase difference between output clock and refclk is variable when restart AD9517-3?

Category: Datasheet/Specs
Product Number: AD9517-3ABCPZ

AD9517-3 use external reference clock,the clock is 20M Hz,VCO is set to 1.92G,the frequency division is 16,the Output target frequency is 120M Hz。The Phase-locked marking is right。But the phase difference between  output clock(120M) and refclk(20M) is variable when restart AD9517-3。And  reset AD9517-3 by AD9517-3_pin17_nRESET, the phase difference is larger than power off and restart the module。The question: is it right the uncertain phase difference,What is the range of variation? I need the variable < 0.05ns。

  • HI,

    let me see if I get this issue right:

    - you configure the AD9517-3, provide the 20MHz reference clock, calibrate the VCO and the PLL locks. You could see on the scope the 120MHz output has a certain phase offset relative to the 20MHz reference clock

    -then if you reset the AD9517-3 and start the process again, you find that the 120MHz output has another phase offset relative to the 20MHz reference clock. And you question yourself why is this happening.

    Please send me the stp file you output from the evaluation software when you created the configuration you are playing with.

    Let's say you configured the AD9517-3 in this way:

    This is what I believe it happens

    - the VCO output is 1.92GHz, 96 times greater than the 20MHz reference. The PLL feedback divider output clock is brought in phase with the 20MHz reference clock. The user cannot control which VCO edge the feedback divider starts to obtain its 20MHz output.

    - the output divider ratio of 16 is composed by two dividers, the VCO divider, which should be set to 2 or 4 for your application and the distribution divider, which should be set to 8 or respectively, 4. The user cannot control at which VCO edge the first divider starts and at which edge of the VCO divider output the distribution divider starts.

    So there is always an uncertainty of the phase offset between the output clock and the reference clock because of all these 3 dividers. You cannot make them start working on the same VCO output edge.

    The uncertainty of this phase offset should be of 96 VCO cycles because the output dividers can align themselves to any of these edges, which means a 20MHz clock cycle.

    My proposal is for you to use the AD9520-3 instead because this chip has an internal zero delay mode.

    If you configure the AD9520-3 as above:

    - the PLL feedback divider output clock (equal to 6) is guaranteed to be in phase with the 20MHz reference clock when the PLL locks

    -the OUT0=120MHz is the input to the PLL feedback divider, which makes the 120MHz clock to be always in phase with the 20MHz reference clock.


  • Thank you very much for your answer. It's very helpful. Can we adjust the phase by changing the frequency division, like phase lock control?

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