ADCLK905
Recommended for New Designs
The ADCLK905 (one input, one output), ADCLK907 (dual one
input, one output), and ADCLK925 (one input, two outputs) are
ultrafast clock/data buffers fabricated...
Datasheet
ADCLK905 on Analog.com
Is it possible to open the Vt pin and input LVDS?
Or connect 50 Ω to the Vt pin as a Y termination,
Can you enter LVPECL?
Hi,
The recommended input termination for differential input signals for ADCLK905 is shown in Figure 28. Both voltage swings of LVDS (0.4Vpp) and LVPECL (0.2Vpp) is within the ADCLK905 specification of 0.2 to 2.8Vpp input differential range.
Best regards,
Mark
Hi,
AD9689-2000EBZ board has ADCLK905 mounted,
Used as a buffer for SYSREF to the FPGA board.
I want to put a pulse signal into SYSREF, so
I want to change from AC coupling to DC coupling.
Is the method I suggested possible?
