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Design support for HMC698

Category: Hardware
Product Number: HMC698

I Have used HMC698 for the following specs: 

1) Reference Frequency: 100MHz (-155dBc/Hz @ 1KHz offset)
2) VCO to be used is:  CVCO55CC-4000-4000 (Crystek Corporation)
3) Loop Bandwidth: 100KHz
4) PLL Total Phase Noise at 4GHz: -110dBc/Hz @ 1KHz offset
5) Max power supply to OpAmp: +5V (LT6200 is used)
6)Synthesizer: HMC698
1) I have used LT6200 as an Active loop filter. Is it okay if I provide +5V as VCC? or should i provide -5V also along with +5V?  and please let me know whether the schematic followed is correct. I have attached the snapshot of the same.
2) Also I have used the N counter values as 100100 (N0-N5) and 00(S0-S1) against the division ratio (n)=40 and Prescaler value=4. Is this logic Correct?
3) I have tried simulating PLL performance in both ADLSim and Hittie PLL Design tool. But, the results are different. Could you please evaluate the correctness of .pllsim file attached in zip for the above mentioned specs.