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Design support for HMC698

Category: Hardware
Product Number: HMC698

I Have used HMC698 for the following specs: 

1) Reference Frequency: 100MHz (-155dBc/Hz @ 1KHz offset)
2) VCO to be used is:  CVCO55CC-4000-4000 (Crystek Corporation)
3) Loop Bandwidth: 100KHz
4) PLL Total Phase Noise at 4GHz: -110dBc/Hz @ 1KHz offset
5) Max power supply to OpAmp: +5V (LT6200 is used)
6)Synthesizer: HMC698
1) I have used LT6200 as an Active loop filter. Is it okay if I provide +5V as VCC? or should i provide -5V also along with +5V?  and please let me know whether the schematic followed is correct. I have attached the snapshot of the same.
 
2) Also I have used the N counter values as 100100 (N0-N5) and 00(S0-S1) against the division ratio (n)=40 and Prescaler value=4. Is this logic Correct?
3) I have tried simulating PLL performance in both ADLSim and Hittie PLL Design tool. But, the results are different. Could you please evaluate the correctness of .pllsim file attached in zip for the above mentioned specs.
  • 1) I have used LT6200 as an Active loop filter. Is it okay if I provide +5V as VCC? or should i provide -5V also along with +5V?

    Hi Aishwarya,
    Yes +5V works fine, the LT6200 is Rail-to-Rail Input/output, so you can use between 2.5V to 12.6V as well as +-5V. More information on the LT6200/LT6201 datasheet page 1. 

    2) Also I have used the N counter values as 100100 (N0-N5) and 00(S0-S1) against the division ratio (n)=40 and Prescaler value=4. Is this logic Correct?

    This should work fine in this case.

    3) I have tried simulating PLL performance in both ADLSim and Hittie PLL Design tool. But, the results are different. Could you please evaluate the correctness of .pllsim file attached in zip for the above mentioned specs.

    Based on the design file you provided, there is no issue with your design specifications. I only just made some adjustments on the Phase Noise floor for the VCO from -130 dBc/Hz to -160dBc/Hz and few tweaks on the components you may find helpful as it lowers Jitter value and slightly improves the performance. Can you further clarify what difference you are noticing between the .simPLL and H Design file or the problem you are trying to solve. Thanks
     Design2.zip

  • Hi with respect to the design file attached, is there any provision in PLLSim tool to insert a Frequency doubler, HMC575 and check the phase noise at the output of it? Also how to simulate the phase noise for the entire system which includes power divider and few Band pass filters?

    2625.Design2.zip

  • Hi Aishwarya, At the moment the SimPLL does not have a provision for Frequency doubler only a frequency divider . The SimPLL only caters for PLLs, you will not be able to simulate an entire system that includes a divider and Band pass filters. 
    Cheers

  • Hi,

    With Reference to the attcahed image, I am using LT6200 as active loop filter for my PLL design and HMC698 is my synthesizer. I have following queries regarding PCB layout:

    1) Should the PFD_OUT (+ and -), to be routed as 100 ohm differential lines or 50 ohm Traces? or is it okay if i route them as regular voltage traces?

    2) If the above mentioned lines are routed as 100 ohm differential lines or as a 50 ohm trace, then what about the feed back path of filter? Should that also be a 50 ohm RF trace?

    3) The output of active filter (Vtune to VCO), also should be routed as 50 ohm trace? or is it okay if i use a regular voltage trace?

  • Hi Aishwarya, for this type of input/output type I am sure a regular trace will do just fine. It is mostly typical to use "impedance" traces in high frequency generating scenario.