Is there a diagram available that can show the topology of the PLL0 loop filter when internal mode is selected identifying the 3 adjustable components? (RPOLE2, RZERO, CPOLE1 and fixed CPOLE2).
Also, the datasheet states to attach a 4.7nF capacitor between LF and LDO_BYP pins. Does this capacitor also form part of the loop filter when internal mode is selected?