Post Go back to editing

hmc7044: clk and sysref hasn't a fix phase relation from sysref_request to sysref_request

Category: Software
Product Number: hmc7044
Software Version: 2019_r2

After a reseed request the relation between clock and sysref is fix, I could run the reseed_request multiple times. Always the same relation.

echo 1 > /sys/bus/iio/devices/iio:device1/reseed_request

If I run sysref_request multiple times, the relation clock and sysref seems random.  (hmc7044 reg 0x005A = 1)

echo 1 > /sys/bus/iio/devices/iio:device1/sysref_request

If I set pulse generator mode to Continuous mode (hmc7044 reg 0x005A = 7), the phase relation is always the same.

Question: How could I send extra sysref pulse without stopping the clock (reseed_request stops the clock) with fix phase relation. What I expect is that I have to sync the hmc7044 one time after startup with the reseed_request and could send sysref pulses afterwards.

dtb configurations (I use channel 8 and 9 for the clock and sysref comparison):

hmc7044_fmc: hmc7044-fmc@2 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adi,hmc7044";
		reg = <2>;
		spi-max-frequency = <10000000>;

		adi,pll1-clkin-frequencies = <240000000 240000000 0 0>;
		adi,pll1-ref-prio-ctrl = <0xE5>; /* prefer CLKIN1 */

		adi,clkin0-buffer-mode  = <0x09>;
		adi,clkin1-buffer-mode  = <0x09>;
		adi,sync-pin-mode = <1>;

		adi,pll1-loop-bandwidth-hz = <200>;

		adi,vcxo-frequency = <240000000>;

		adi,pll2-output-frequency = <2880000000>;

		adi,jesd204-max-sysref-frequency-hz = <1000000>;
		adi,jesd204-desired-sysref-frequency-hz = <2560000>;
		adi,hmc-two-level-tree-sync-en;
		adi,sysref-timer-divider = <3840>;
		adi,pulse-generator-mode = <7>;

		adi,oscin-buffer-mode = <0x15>;

		adi,gpi-controls = <0x00 0x00 0x00 0x11>;
		adi,gpo-controls = <0x1f 0x2b 0x00 0x00>;

		adi,high-performance-mode-clock-dist-enable;
		adi,high-performance-mode-pll-vco-enable;

		clock-output-names =
			"hmc7044_fmc_out0_DEV_REFCLK_C", "hmc7044_fmc_out1_DEV_SYSREF_C",
			"hmc7044_fmc_out2_DEV_REFCLK_D", "hmc7044_fmc_out3_DEV_SYSREF_D",
			"hmc7044_fmc_out4_JESD_REFCLK_TX_OBS_CD", "hmc7044_fmc_out5_JESD_REFCLK_RX_CD",
			"hmc7044_fmc_out6_FPGA_SYSREF_TX_OBS_CD","hmc7044_fmc_out7_FPGA_SYSREF_RX_CD",
			"hmc7044_fmc_out8", "hmc7044_fmc_out9",
			"hmc7044_fmc_out10", "hmc7044_fmc_out11",
			"hmc7044_fmc_out12", "hmc7044_fmc_out13";

		hmc7044_fmc_c0: channel@0 {
			reg = <0>;
			adi,extended-name = "DEV_REFCLK_C";
			adi,divider = <12>;	// 245760000
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
			adi,coarse-digital-delay = <0>;	/* 15 */
		};
		hmc7044_fmc_c1: channel@1 {
			reg = <1>;
			adi,extended-name = "DEV_SYSREF_C";
			adi,divider = <3840>;	// 768000
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
			adi,control0-rb4-enable;
			adi,force-mute-enable;
			adi,startup-mode-dynamic-enable;
			adi,high-performance-mode-disable;
			adi,driver-impedance-mode = <HMC7044_DRIVER_IMPEDANCE_100_OHM>;
		};
		hmc7044_fmc_c2: channel@2 {
			reg = <2>;
			adi,extended-name = "DEV_REFCLK_D";
			adi,divider = <12>;	// 245760000
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
			adi,coarse-digital-delay = <0>;	/* 15 */
		};
		hmc7044_fmc_c3: channel@3 {
			reg = <3>;
			adi,extended-name = "DEV_SYSREF_D";
			adi,divider = <3840>;	// 768000
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
			adi,control0-rb4-enable;
			adi,force-mute-enable;
			adi,startup-mode-dynamic-enable;
			adi,high-performance-mode-disable;
			adi,driver-impedance-mode = <HMC7044_DRIVER_IMPEDANCE_100_OHM>;
		};
		hmc7044_fmc_c4: channel@4 {
			reg = <4>;
			adi,extended-name = "JESD_REFCLK_TX_OBS_CD";
			adi,divider = <12>;	// 245760000
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
			adi,coarse-digital-delay = <11>;	/* 0 */
		};
		hmc7044_fmc_c5: channel@5 {
			reg = <5>;
			adi,extended-name = "JESD_REFCLK_RX_CD";
			adi,divider = <12>;	// 245760000
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
		};
		hmc7044_fmc_c6: channel@6 {
			reg = <6>;
			adi,extended-name = "FPGA_SYSREF_TX_OBS_CD";
			adi,divider = <3840>;	// 768000
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
			adi,control0-rb4-enable;
			adi,force-mute-enable;
			adi,startup-mode-dynamic-enable;
			adi,high-performance-mode-disable;
		};
		hmc7044_fmc_c7: channel@7 {
			reg = <7>;
			adi,extended-name = "FPGA_SYSREF_RX_CD";
			adi,divider = <3840>;	// 768000
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
			adi,control0-rb4-enable;
			adi,force-mute-enable;
			adi,startup-mode-dynamic-enable;
			adi,high-performance-mode-disable;
		};
		hmc7044_fmc_c8: channel@8 {
			reg = <8>;
			adi,extended-name = "hmc7044_fmc_out8";
			adi,divider = <12>;	// 240000000
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
			adi,coarse-digital-delay = <11>;	/* 0 */
		};
		hmc7044_fmc_c9: channel@9 {
			reg = <9>;
			adi,extended-name = "hmc7044_fmc_out9";
			adi,divider = <3840>;	// 768000
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
			adi,control0-rb4-enable;
			adi,force-mute-enable;
			adi,startup-mode-dynamic-enable;
			adi,high-performance-mode-disable;		
		};