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HMC7044 100MHz input reference clock for 122.88MHz VCXO

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Product Number: HMC7044

Hi,

As shown in the picture below, I use a 122.88MHz VCXO for PLL1. But my signal generator only gives a reference clock of 100MHz so I use that 100MHz reference clock for the HMC7044. My problem is that the PLL1 did not lock. I configure the PLL1 as below:

1.  CLKIN0 Prescaler  = 2 (0x001C = 0x02)

2. N1 divider = 1536 (0x0027 = 06, 0x0026 = 00)

3. R1 divider = 625 (0x0022 = 02, 0x0021 = 71)

4. Timer threshold = 31 (0x0028 = 0x1F)

for this configuration, the PD1 frequency was 80 kHz (Was it too small?). I check the PLL1 status register (0x007C) it switches between 0x4E and 0xCE. that means the PLL1 is near lock but it never locks. Can you help me out with this problem?

Thank you in advance.

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  • Hi,

    I tried your configuration with the evaluation board, and I see that PLL1 is locking. Setting the PLL1 lock timer to 31 makes it very long to declare lock. You can try to decrease it to ~20 and give some timeout before reading the Reg0x7C. Are you using the same loop filter and VCXO that is used on EVB? If not, the loop filter in your design may not be stable. Did you simulate it with ADISIMCLK?

    Kudret

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