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Avoiding feedback loops in AD9545/AD9546 system clock compensation

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Product Number: AD9546

I have a setup with a low-frequency (100 Hz) synchronization marker embedded in a high-frequency (10 MHz) clock reference locked to GPS. I would like to use the high-frequency reference for system clock compensation, in particular to measure skew using the skew measurement unit between the tagged 100 Hz synchronization markers on various inputs to the AD9546, including the input with the high-frequency reference clock. This seems like it involves applying compensation to the TDCs associated with the synchronization markers based on the high-frequency reference being measured by the same TDCs. This seems like a recipe for a feedback loop. Is there an obvious solution to this that I am missing?



Clarify wording
[edited by: nwhitehorn at 4:49 PM (GMT -4) on 15 Sep 2022]
  • Hi,

    You can use the 10MHz carrier as the reference to the AuxDPLL to compensate the system clock wonder at TDCs.

    Then you can use the 100Hz tags as clock inputs to the skew measurement.

    About the fact that the system clock compensation is applied to TDCs and one of these TDCs is used as reference to the AuxDPLL:

    The AuxDPLL is designed such that the corrections resident in the compensated TDC that drives the AuxDPLL are removed before entering the correction loop, which mitigates a positive feedback scenario.

    Petre

  • The AuxDPLL is designed such that the corrections resident in the compensated TDC that drives the AuxDPLL are removed before entering the correction loop, which mitigates a positive feedback scenario.

    Thank you much! I hadn't appreciated this detail -- that solves the problem completely.

    We have been super pleased with this part, as well. It's a fantastic tool.