Hello,
I'm evaluating the AD9542. I've attached my CSO file and an image of my lab setup. The issue I've found is that two outputs of the same frequency on the same PLL channel have a large phase offset between them. The outputs are single ended, CML mode, 7.5mA, ac coupled to the o-scope with 50 ohm probes. Could you please advise?
HI,
I looked at the cso file you sent. You set DPLL0 to execute auto synchronization of the outputs after the DPLL locks in frequency.
So unless the AD9542 deemed one of REFA or REFB valid, selected one of the two profiles you enabled on lock onto that reference, there should not have been any output before the DPLL0 has locked in frequency. After that, the outputs should have come in phase as the sync operation resets the distribution dividers.
If you did not apply a REFA or REFB clock, after power up, the DPLL0 should have entered free run and no clock should have been generated at all Channel 0 outputs.
You set REFA and REFB to be dc coupled 1.8V CMOS inputs. The AD9542 eval board has indeed REFB dc coupled, but REFA is ac coupled. To work, you should replace the capacitors C300 and C301 with 0ohm resistors and take out R306=49.9ohm, which may load the CMOS input and lower the high level. On REFB, you should also R318=49.9ohm for the same reasons.
I suggest make these changes, power down the board. Shut down ACE. Power up the board, connect it to PC. Then launch ACE and load the cso file. Apply REFA or REFB. Click Apply Changes, then Cal All. The DPLL0 should lock and the channel 0 outputs should be generated in phase.
In my case, I just changed REFA to be ac coupled and I applied 10MHz, 3dBm from a signal generator. The DPLL0 and DPLL1 locked right away and I saw OUT0BN and OUT0CN on the scope being in phase.
Petre
