Dear ADI support,
Similar to the graph provided in Figure 21 of the AD9515 datasheet, do you have a phase noise plot for a divide by 10 configuration, 100MHz in with 10MHz out? Thank you,
Jerry
AD9515
Recommended for New Designs
The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other...
Datasheet
AD9515 on Analog.com
Dear ADI support,
Similar to the graph provided in Figure 21 of the AD9515 datasheet, do you have a phase noise plot for a divide by 10 configuration, 100MHz in with 10MHz out? Thank you,
Jerry
Hi,
I recommend using the ADIsimCLK simulation tool to obtain it phase noise plot. You can introduce the phase noise of the 100MHz input and simulate the phase noise of the OUT1=10MHz CMOS output.
You can download the ADIsimCLK tool from here: https://www.analog.com/en/design-center/adisimclk.html
Petre