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HMC7044 Subharmonics FS/2 spur Reg.

Category: Hardware
Product Number: HMC7044,AD9208

HI!

I am using AD9208 and HMC7044 together.

We are seeing  spur in the FFT of the ADC output. the spur follows the Fs/2-Fin pattern and is -50dBc down which is greatly affecting the performance of AD9208.

As AD9208 is not an interleaving ADC, On inspecting the Clock input (i.e, Clock output from HMC7044), Fs/2 sub harmonics is present at a level of -40dBc down from Sampling clock of 2.94912GHz which is affecting our ADC performance.

Please find the attached HMC7044 Config file and HMC7044 Clock spectrum showing FS(2949.12MHz) and FS/2(1474.56MHz) spur.

Address	Data
0x0000	0x01
0x0000	0x00
0x00A0	0xDF
0x00A5	0x06
0x00A8	0x06
0x00B0	0x04
0x0001	0x60
0x0003	0xB
0x0004	0x7F
0x0005	0x04
0x000A	0x00
0x000B	0x00
0x000C	0x01
0x000D	0x00
0x000E	0x07
0x0014	0xC9
0x0016	0x09
0x001A	0x0F
0x001C	0x01
0x001D	0x4
0x001E	0x01
0x001F	0x04
0x0020	0x04
0x0021	0xFA
0x0022	0x0
0x0026	0x0
0x0027	0xC
0x0028	0x1F
0x0029	0x10
0x002A	0x0F
0x0032	0x01
0x0033	0x01
0x0034	0x00
0x0035	0x18
0x0036	0x00
0x0037	0x0F
0x0046	0x00
0x0047	0x00
0x0048	0x00
0x0049	0x00
0x0050	0x1D
0x0051	0x29
0x0052	0x35
0x0053	0x00
0x0054	0x01
0x00C8	0x91
0x00C9	0x1
0x00CA	0x00
0x00CB	0x00
0x00CC	0x00
0x00CD	0x00
0x00CE	0x00
0x00CF	0x00
0x00D0	0x08
0x00D2	0x90
0x00D3	0x00
0x00D4	0x0F
0x00D5	0x00
0x00D6	0x00
0x00D7	0x00
0x00D8	0x00
0x00D9	0x00
0x00DA	0x30
0x00DC	0x91
0x00DD	0x1
0x00DE	0x00
0x00DF	0x00
0x00E0	0x00
0x00E1	0x00
0x00E2	0x00
0x00E3	0x00
0x00E4	0x01
0x00E6	0x90
0x00E7	0x00
0x00E8	0x0F
0x00E9	0x00
0x00EA	0x00
0x00EB	0x00
0x00EC	0x00
0x00ED	0x00
0x00EE	0x30
0x00F0	0x91
0x00F1	0x10
0x00F2	0x00
0x00F3	0x00
0x00F4	0x00
0x00F5	0x00
0x00F6	0x00
0x00F7	0x00
0x00F8	0x11
0x00FA	0x90
0x00FB	0x00
0x00FC	0x0F
0x00FD	0x00
0x00FE	0x00
0x00FF	0x00
0x0100	0x00
0x0101	0x00
0x0102	0x30
0x0104	0x91
0x0105	0x10
0x0106	0x00
0x0107	0x00
0x0108	0x00
0x0109	0x00
0x010A	0x00
0x010B	0x00
0x010C	0x01
0x010E	0x90
0x010F	0x00
0x0110	0x0F
0x0111	0x00
0x0112	0x00
0x0113	0x00
0x0114	0x00
0x0115	0x00
0x0116	0x30
0x0118	0x91
0x0119	0x10
0x011A	0x00
0x011B	0x00
0x011C	0x00
0x011D	0x00
0x011E	0x00
0x011F	0x00
0x0120	0x11
0x0122	0x90
0x0123	0x00
0x0124	0x0F
0x0125	0x00
0x0126	0x00
0x0127	0x00
0x0128	0x00
0x0129	0x00
0x012A	0x30
0x012C	0x91
0x012D	0x10
0x012E	0x00
0x012F	0x00
0x0130	0x00
0x0131	0x00
0x0132	0x00
0x0133	0x00
0x0134	0x11
0x0136	0x90
0x0137	0x00
0x0138	0x0F
0x0139	0x00
0x013A	0x00
0x013B	0x00
0x013C	0x00
0x013D	0x00
0x013E	0x30
0x0140	0x90
0x0141	0x0C
0x0142	0x00
0x0143	0x00
0x0144	0x00
0x0145	0x00
0x0146	0x00
0x0147	0x00
0x0148	0x11
0x014A	0x91
0x014B	0x10
0x014C	0x0
0x014D	0x0
0x014E	0x00
0x014F	0x00
0x0150	0x00
0x0151	0x00
0x0152	0x11
0x0001	0x66
0x0001	0x64
0x0001	0xE4

Please help us in reducing this spur level so that we can achieve the ADC performance claimed in AD9208 DS.

Thanks in-advance,

Deva

Parents
  • Hi, I have moved this to the Clocks and Timing forum. FormerMember  should be able to help

  • Hi,

    It is expected to see fs/2 spur at the output of HMC7044 output as div by 1 block uses div by 2 logic. 

    I am seeing around -50 dBc at HMC7044 EVB output, the difference might be related with decoupling caps and/or layout. 

    If you change channel output MUX to fundamental instead of div by 1, you should see than spur level decreases. This will result a constant phase difference between the device clock and SYSREF clocks which can be calibrated out with digital delay and analog delay blocks. 

    Kudret 

Reply
  • Hi,

    It is expected to see fs/2 spur at the output of HMC7044 output as div by 1 block uses div by 2 logic. 

    I am seeing around -50 dBc at HMC7044 EVB output, the difference might be related with decoupling caps and/or layout. 

    If you change channel output MUX to fundamental instead of div by 1, you should see than spur level decreases. This will result a constant phase difference between the device clock and SYSREF clocks which can be calibrated out with digital delay and analog delay blocks. 

    Kudret 

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