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AD9528 - muting outputs without losing output divider synchronisation

Category: Hardware
Product Number: AD9528

Hello. 

Is there any way to mute or power down the AD9528 clock outputs without also powering down the output divider?  I have found that the output dividers lose their phase relationship if I use the channel power down registers 0x0501 or 0x0502 to disable and then enable an output.

Ideally, I would like the outputs to maintain their phase relationship when the outputs are turned off then on and I do not want to resync the dividers afterwards. 

So if there is a register that can just turn off the output buffer that would be ideal!

Thanks for the help.

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  • Hi,

    The only way I found is to set the bit 0 (Sync outputs) in register 0x32A to 1. This makes the output drivers to stop generating the output clocks (the data sheet speaks of disabling them at page 31). Then, when you want to enable back the outputs, clear to 0 the bit 0 in register 0x32A. The outputs are generated in a synchronized way. It is basically the sync command.

    Petre

  • Hi Petre.

    Thanks for the information on Sync. Unfortunately I think using Sync changes the absolute phase of the divided output clocks relative to the VCO RF divider, as a different VCO RF divider edge is used depending on when Sync is released. 

    In my application I need to maintain the phase of all the output clocks relative to the real world, after the first initial divider sync done on power up.  It appears that powering down/up the outputs changes the divider phase, as as does issuing another sync. 

    Not a huge problem as I can leave the outputs up.  I was just hoping to save a bit of power and not enable unnecessary outputs when they were not required.

  • Hi,

    regarding your concern that "using Sync changes the absolute phase of the divided output clocks relative to the VCO RF divider, as a different VCO RF divider edge is used depending on when Sync is released"

    If you can configure the AD9528 PLL2 in an equivalent internal zero delay mode, than this guarantees the outputs will be in phase to the reference clock into the PLL2 PFD any time a sync operation is done. This fulfills your goal.

    Please take a look at the figure above: The PLL2 N2 feedback divider is reset together with all the distribution dividers when a sync is executed. The key is to make N2 equal to the output divider. In this way, the output clock is equal to the feedback clock at PLL2 PFD, which is equal to the VCXO_IN/R1(*2), the input clock into the PFD. Which means you configured PLL2 in an equivalent internal zero delay mode.

    Petre

  • Hi Petre. 

    Thank you for your detailed reply and the assistance.

    Apologies, I didn't explain things very well previously.

    In the picture above, trace 2 illustrates the divided output after I have synchronised the dividers once on power up. 

    Trace 3 shows an example of what happens if I mute the output, then enable it and issue a divider sync.  The output is now out of phase with the original output (trace 2). 

    I was hoping there would be some way to disable the output whilst maintaining the original phase, i.e. as if the output had just been physically disconnected and reconnected.  In my application the rising edges of the divided output is used as a timestamp, so the rising edges must always occur with the correct periodicity. With trace 3 the rising edge has been shifted by half a cycle, resulting in a half cycle timestamp error.

    It's not an issue if the AD9528 can't do this.  I just wanted to check if there was something I had missed in the datasheet.

    Hope that makes sense!  

  • HI,

    I understand. This is why I recommended to study if you can configure PLL2 in internal zero delay  mode. In this configuration, executing a sync command will make the outputs to always come out with the phase of the reference clock at PFD. The disadvantage of this is that setting the bit 0 (Sync outputs) in register 0x32A to 1 stops all outputs, so you cannot manipulate only one output.

    I also played today in the lab and I can confirm that even in the internal zero delay mode, powering down one output and powering it back up may bring the output out of phase with the other outputs (and with the PFD input). A sync is still necessary. Also, disabling/reenabling the LDO of that channel has the same effect. A sync operation is necessary.

    Petre

Reply
  • HI,

    I understand. This is why I recommended to study if you can configure PLL2 in internal zero delay  mode. In this configuration, executing a sync command will make the outputs to always come out with the phase of the reference clock at PFD. The disadvantage of this is that setting the bit 0 (Sync outputs) in register 0x32A to 1 stops all outputs, so you cannot manipulate only one output.

    I also played today in the lab and I can confirm that even in the internal zero delay mode, powering down one output and powering it back up may bring the output out of phase with the other outputs (and with the PFD input). A sync is still necessary. Also, disabling/reenabling the LDO of that channel has the same effect. A sync operation is necessary.

    Petre

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