AD9542 Temperature Compensation

Hi,

I do not have this data. You would have to contact Taitien to obtain the typical fractional frequency error , then convert it to the fractional period error and then calculate the coefficients that best fit the FPE data. The problem I see is that this method compensates the typical crystal resonator induced effect, not the particular crystal resonator used to clock the AD9542.

I recommend instead to using a OCXO  to drive the auxiliary DPLL and use the compensation method 3 to compensate the system clock.

Petre

Hi,

I do not have this data. You would have to contact Taitien to obtain the typical fractional frequency error , then convert it to the fractional period error and then calculate the coefficients that best fit the FPE data. The problem I see is that this method compensates the typical crystal resonator induced effect, not the particular crystal resonator used to clock the AD9542.

I recommend instead to using a OCXO  to drive the auxiliary DPLL and use the compensation method 3 to compensate the system clock.

Petre

Thanks. Imagine I am using a crystal oscillator for good phase noise as sys clock ref and both the DPLLs are driven from REF A and REF A is connected to a stable and temp independent source (~0.25 ppm). Would enabling system clock compensation from an OXCO on REF B accomplish anything?  Or is it only useful if the stability of the OXCO is much better than the stability of the sys clock and also the reference source for the DPLL? 

Hi,

we recommend to use a crystal resonator of 52MHz to obtain the best phase noise performance on the AD9542 outputs. The reason is that the AD9542 maintaining amplifier creates a reference clock to the system clock PLL that has a 50% duty cycle. You can use a crystal resonator with a higher frequency as well, but we saw the phase noise improvements are not significant.

Also, the doubler has also an important contribution to obtaining the best phase noise. The doubler works best when the system clock PLL reference has 50% duty cycle.

If you use an oscillator as the system clock PLL reference, the phase noise of the outputs is not as good. The oscillators have usually a guaranteed 45% to 55% duty cycle, not 50%, and this influences negatively the phase noise. Also the doubler does not function well with such duty cycles.

So, we then need to use the system clock compensation to eliminate the effect of the crystal resonator wonder on the DPLLs, Aux NCOs, TDCs. I recommend using a 10MHz (i.e relatively low frequency, therefore low(er) cost) OCXO as the reference clock to the Auxiliary DPLL and use this AuxDPLL to compensate the system clock effects (compensation method 3 method in the data sheet)

The system clock compensation makes sense when very low loop bandwidth DPLL applications are pursued, like the 1PPS ones. By the way, the AD9542 does not support 1PPS applications, the AD9544 and the AD9545 do.

Another application in which the system clock compensation would make sense is when someone needs the DPLLs to function very accurately (as accurate as the OCXO) in freerun/holdover.

I do not know other cases in which a stable system clock (and therefore a need to compensate it) is necessary. 

Please use the AD9545 rev C as reference for the AD9542 block components.

Petre