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Output shape issue with AD9542

Category: Software
Product Number: AD9542

Issue with creating clean 122.88 MHz clock signal using AD9542. Using valid 10 MHz ref input. I have attached cso file, screenshots of o'scope and of ACE software. In ACE, the mux in DPLL0 and DPLL1 is highlighted red, not sure where that error is coming from. I am using the AD9542 eval board. Spectrum analyzer signal output is just as bad, with many harmonics. Would appreciate any help.  The CSO file had issues uploading, had to send as a txt file. Thanks, Alex


  • Hi Alex,

    First, thanks for providing the information that should help us resolve the issue.  Don't worry about the red mux highlight.  The max TDC rate is 200kHz and sometimes frequencies of 200kHz are flagged due to round-off errors in the error checking.  The GUI indication that all PLLs are locked is a good sign that you are very close.  Congrats!

    Regarding your real problem of the output looking bad, there is some additional information that I'd like to get.  I'm hoping to get information from you to resolve the problem quickly since I won't be able to run tests in the lab until Friday.

    1) Are your outputs programmed for HCSL or CML?  Since you are only swinging 100mVpp, I'm guessing the problem is an improper output termination.  CML requires 50ohm terminations to supply.  HCSL requires 50ohm terminations to ground.  The eval board termination is controlled by jumpers (Ex. P302).  These are typically setup for an LVDS/CML type output swing - See Figure 34 in AD9542 datasheet.  My quick glance at your txt file indicates you have the default output programming of HCSL.  Go into the output driver and change the format to CML and the output should appear as you would expect.

    2) If the above doesn't work...Slow the output down 10x for roughly a 12MHz output, what does the output look like?  This will help determine if there is a transient problem or a termination issue.

  • As another follow up, is there a way to measure the time for the DPLLs to lock to the reference signal? Would like to compare DPLL lock time vs loop bandwidth

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