AD9528: Does PLL1 really need to be locked when PLL2 is in Locked State ?

Question

Hi Team ADI, 
 I am working on AD9528 and I am giving reference from AD9545 to AD9528 VCXO. 
 -> AD9545 PLLs are locked as expected 
 -> AD9528 PLL2 is locked as expected but PLL1 is not locked because of N1 divider. If I make N1 = 8 then PLL1 gets lock. 
 I've few queries on this. Could you please clarify this ? 
 1) Does it really matter that PLL1 must be locked ? 
 2) What will be the impact when I choose different value for out-div and N2 i.e. (N2 = out-div) ? 
 3) For reduction of high in-band noise, input frequency to PLL1/PLL2 (PFD) must be higher that mean to me "N1 and N2 divider 
 must have greater value". Is it true ?

Sincere Regards, 
 MKS

pminc48 · Accepted Answer

Hi, I replicated the AD9528 eval software image you provided and I have certain settings that are different than yours. I, for example, use the PLL2 charge pump current at its max current, 893.5uA. You use a lower value, 805 uA. This means a lower PLL2 loop bandwidth, which may be what you in the end wanted. You do not have the registers 0x303 to 0x329 set. These are registers that manage the outputs, so definitely what you have on your AD9528 eval software figure does not match the register values. Anyway, please find attached the stp file I created based on your figure and the ADIsimCLK file I created based on these settings. Please use this file to see the behavior of the AD9528. Take out the txt extension before using them. I recommend making changes first in the eval software, see if they are accepted and then introduce them into the ADIsimCLK to study their effects. AD9528_setup2.clk.txt Fullscreen AD9528_setup2.stp.txt Download

product = AD9528 softwareversion = 1.0.0.3

-- PLL1 -- - Ref A - Powered Down - Ref B - Powered Down - Clk In - Osc Freq: 245.76 MHz N1: 1 PFD Freq: 245.76 MHz ------------------ -- PLL2 -- Input Freq: 245.76 MHz R2: /1 PFD Freq: 245.76 MHz N2: 4 Dist Freq: 983.04 MHz M: 4 VCO Freq: 3.93216 GHz ---------------------- -- SysRef -- Source: Internal Generation Freq: 512.0 kHz ---------------------- -- Distribution -- Input Source: PLL2 Input Freq: 983.04 MHz - Out 0 - Input Source: Sysref Output Freq: 512.0 kHz - Out 1 - Input Source: D1 D1:4 Output Freq: 245.76 MHz - Out 2 - Input Source: D2 D2:4 Output Freq: 245.76 MHz - Out 3 - Input Source: D3 D3:4 Output Freq: 245.76 MHz - Out 4 - Input Source: D4 D4:5 Output Freq: 196.608 MHz - Out 5 - Input Source: Sysref Output Freq: 512.0 kHz - Out 6 - Input Source: D6 D6:5 Output Freq: 196.608 MHz - Out 7 - Input Source: Sysref Output Freq: 512.0 kHz - Out 8 - Input Source: D8 D8:5 Output Freq: 196.608 MHz - Out 9 - Input Source: Sysref Output Freq: 512.0 kHz - Out 10 - Input Source: D10 D10:5 Output Freq: 196.608 MHz - Out 11 - Input Source: Sysref Output Freq: 512.0 kHz - Out 12 - Input Source: PLL1 Output Freq: 245.76 MHz - Out 13 - Input Source: PLL1 Output Freq: 245.76 MHz ---------------------- Register (Hex), Value (Hex), Value (Dec) 0x0, 0x00, 0 0x1, 0x00, 0 0x3, 0x05, 5 0x4, 0xFF, 255 0x5, 0x00, 0 0x6, 0x03, 3 0xa, 0x00, 0 0xb, 0x00, 0 0xc, 0x56, 86 0xd, 0x04, 4 0xf, 0x00, 0 0x100, 0x01, 1 0x101, 0x00, 0 0x102, 0x01, 1 0x103, 0x00, 0 0x104, 0x01, 1 0x105, 0x00, 0 0x106, 0x0C, 12 0x107, 0x00, 0 0x108, 0x00, 0 0x109, 0x00, 0 0x10a, 0x00, 0 0x10b, 0x00, 0 0x200, 0xFF, 255 0x201, 0x04, 4 0x202, 0x03, 3 0x203, 0x00, 0 0x204, 0x04, 4 0x205, 0x2A, 42 0x206, 0x00, 0 0x207, 0x00, 0 0x208, 0x03, 3 0x209, 0x00, 0 0x300, 0x40, 64 0x301, 0x00, 0 0x302, 0x04, 4 0x303, 0x00, 0 0x304, 0x00, 0 0x305, 0x03, 3 0x306, 0x00, 0 0x307, 0x00, 0 0x308, 0x03, 3 0x309, 0x00, 0 0x30a, 0x00, 0 0x30b, 0x03, 3 0x30c, 0x00, 0 0x30d, 0x00, 0 0x30e, 0x04, 4 0x30f, 0x40, 64 0x310, 0x00, 0 0x311, 0x00, 0 0x312, 0x00, 0 0x313, 0x00, 0 0x314, 0x04, 4 0x315, 0x40, 64 0x316, 0x00, 0 0x317, 0x00, 0 0x318, 0x00, 0 0x319, 0x00, 0 0x31a, 0x04, 4 0x31b, 0x40, 64 0x31c, 0x00, 0 0x31d, 0x00, 0 0x31e, 0x00, 0 0x31f, 0x00, 0 0x320, 0x04, 4 0x321, 0x40, 64 0x322, 0x00, 0 0x323, 0x00, 0 0x324, 0x20, 32 0x325, 0x00, 0 0x326, 0x00, 0 0x327, 0x20, 32 0x328, 0x00, 0 0x329, 0x00, 0 0x32a, 0x00, 0 0x32b, 0x00, 0 0x32c, 0x00, 0 0x32d, 0x00, 0 0x32e, 0x00, 0 0x400, 0xF0, 240 0x401, 0x00, 0 0x402, 0x18, 24 0x403, 0x91, 145 0x404, 0x04, 4 0x500, 0x10, 16 0x501, 0x00, 0 0x502, 0x00, 0 0x503, 0xFF, 255 0x504, 0xFF, 255 0x505, 0x00, 0 0x506, 0x00, 0 0x507, 0x00, 0 0x508, 0x00, 0 0x509, 0x00, 0 50000000;122880000;245760000;768000 Petre)

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AD9528: Does PLL1 really need to be locked when PLL2 is in Locked State ?