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AD9528: Does PLL1 really need to be locked when PLL2 is in Locked State ?

Category: Software
Product Number: AD9528

Hi Team ADI,

I am working on AD9528 and I am giving reference from AD9545 to  AD9528 VCXO.  

-> AD9545 PLLs are locked as expected

-> AD9528 PLL2 is locked as expected but PLL1 is not locked because of N1 divider. If I make N1 = 8 then PLL1 gets lock.  

I've few queries on this. Could you please clarify this ?

1) Does it really matter that PLL1 must be locked ? 

2)  What will be the impact when I choose different value for out-div and N2  i.e. (N2 = out-div) ? 

3)  For reduction of high in-band noise, input frequency to PLL1/PLL2 (PFD) must be higher that mean to me  "N1 and N2 divider

   must have greater value".  Is it true ? 

Sincere Regards,

MKS



GRMMR
[edited by: MKS3134 at 8:27 AM (GMT -4) on 22 Jul 2022]
Parents
  • HI,

    if you applied a clock from the AD9545 to VCXO_IN pins of the AD9528, then it cannot be that PLL1 had locked. This is impossible because the PLL1 charge pump current has to go to a VCXO, not an AD9545. 

    So my recommendation is to leave PLL1 alone as you do not need it.

      What will be the impact when I choose different value for out-div and N2  i.e. (N2 = out-div) ?

    Right now, on OUT1, you have the distribution divider equal to the PLL2 feedback divider and equal to 4. This means that when you execute a Sync operation, both these dividers are reset simultaneously (see Sync signal applied to N2 divider and all distribution dividers in the figure below) and this makes the outputs of these dividers to be identical. Then, when PLL2 locks, the N2 output is identical to the PLL2 PFD reference,  which in your case is the VCXO clock, so basically you have OUT1 equal to the clock you apply at VCXO_IN pins

    If the N2 and distribution dividers values are different, then you have different clocks that may not be in phase, depending on the actual values of the dividers.

     For reduction of high in-band noise, input frequency to PLL1/PLL2 (PFD) must be higher that mean to me  "N1 and N2 divider  must have greater value".  Is it true ?

    The in band phase noise degradation introduced by a PLL is 20*log10(Fout/Fpfd), so if Fpfd is higher (that is the PLL feedback divider is lower), the phase noise degradation is smaller.

    Play with the ADIsimCLK to see these effects on a real example.

    Petre

  • Hi Sir Petre,

    Thank you so much for the sharing this knowledge. I saw your valuable comments in various post of AD9528 and I appreciate you to give time to comment on my post too. 

    I didn't get few things as I am not very much familiar with AD9528. Please put some light on this when you say:

    >> This is impossible because the PLL1 charge pump current has to go to a VCXO, not an AD9545

    [MKS]: Can you unleash this point as in my post "RED" color configuration was not OK but If I change N1 = 8 , N2 = 5  and M = 5 then I don't see the wrong configuration and I suppose PLL1 must be locked. Though, I didn't check on EVB.  I am attaching image too against this. 

       Changed N1, N2 and M divider setting

    >> when you execute a Sync operation 

    [MKS]: Who gives this sync ?

    >> If the N2 and distribution dividers values are different, then you have different clocks that may not be in phase

    [MKS]:  I understood this point but why will phase because of different dividers even when PLL2 locked.

    >> The in band phase noise degradation introduced by a PLL is 20*log10(Fout/Fpfd), so if Fpfd is higher (that is the PLL feedback divider is lower), the phase noise degradation is smaller.

    [MKS]:  It means to me that feedback divider must be higher so that Fpfd is smaller which gives "higher phase noise degradation" 

     

    Thanks so much for sharing tool as well to check performance. I really thank you Sir Peter.

    Best Regards,

    MKS

  •  I said Hi,

    [MKS]: Can you unleash this point as in my post "RED" color configuration was not OK but If I change N1 = 8 , N2 = 5  and M = 5 then I don't see the wrong configuration and I suppose PLL1 must be locked. Though, I didn't check on EVB.  I am attaching image too against this. 

    PLL1 needs a VCO connected to VCXO_IN pins o function as PLL. You said you connected an AD9545 output clock instead. This is why you cannot use PLL1.

    [MKS]: Who gives this sync ?

    See page 31 in the rev E data sheet.

    [MKS]:  I understood this point but why will phase because of different dividers even when PLL2 locked.

    If N2 and distribution divider values are different, the output clocks are different and they may not be phase aligned. If for example the N2 divider output is 25MHz (40 ns period) and the distribution divider output is 20MHz (50 ns period). Even if I start the clocks in the same moment (because of the sync operation), after the first 40ns, the 25MHz clock starts again while the 20MHz one is still finishing its period. They loose their phase alignment right away.

    But if for example one clock is 25MHz and the other is 50MHz, then every time the 25MHz clock starts a new cycle, that cycle will be phase aligned to the 50MHz clock.

    This is why I said: if the N2 and distribution dividers values are different, then you have different clocks that may not be in phase

    [MKS]:  It means to me that feedback divider must be higher so that Fpfd is smaller which gives "higher phase noise degradation" 

    When I used the term degradation, I meant that adding 20*log10(Fout/Fpfd) to the phase noise is not good. You want this number to be small, which means Fpfd to be as high as possible. This means the feedback divider must be as low as possible.

    Make a search on ADI website for PLL fundamentals tutorials and you'll get several papers you may read to get more insights about PLLs.

    Petre

    Petre

  • Hi Sir Peter,

    Thank you so much for commenting and enlighten us. 

    I have dumped the configuration register of AD9528 and tried in adisimclk but I was expecting timing graph b/w N2 and out divider and it showed me b/w m1 and out divider. I could not understand this.

    I tried setting loop bandwidth based on register setting 0x200 and 0x205 but somehow, I could not end up on correct path.

    Could you please put some light on this ? 

    I've attached my register dump. 

    Sincere Regards,

    MKS

     -------------------------------------------------------------------------------------------------------------------
    refA_Frequency_Hz = 0
    refA_bufferCtrl = 4 ----------------------> Disabled 
    
    refB_Frequency_Hz = 0
    refB_Divider = 1  ------------------------> R Divider
    refB_bufferCtrl = 4-----------------------> Disabled
    
    vcxo_Frequency_Hz = 245760000
    vcxoBufferCtrl = 1
    
    PLL1
    -------
    
    refA_Divider = 1  ------------------------> R Divider
    nDividerPll1 = 1 -------------------------> N Divider
    
    PLL2
    -------
    
    rfDivider = 4  (M Divider)
    n2Divider = 4  (N2 Divider)   
    r1Divider = 1  (R divider) (reg = 0x207)
    totalNdiv = 16 ( M * N2 => 16 == 4*a[=4] + b [=0] )
    
    Sysref
    --------
    sysrefRequestMethod = 0 ------------------------> SPI
    sysrefSource = 2 -------------------------------> Internal
    sysrefPinEdgeMode = 0---------------------------> Lvl Active high
    sysrefPinBufferMode = 4 ------------------------> Disabled ( issue in code)
    sysrefPatternMode = 0 --------------------------> N Shot Pulse
    sysrefDivide = 480------------------------------> K-divider
    sysrefNshotMode =  1 ---------------------------> Pulse
    ----------------------------------------------------------------------------------------------------------------------
    
    
    Register Dump
    ===============
    
    Reg[0]=0x3c
    Reg[1]=0x0
    Reg[0x100]=0x1
    Reg[0x101]=0x0
    Reg[0x102]=0x1
    Reg[0x103]=0x0
    Reg[0x104]=0x0
    Reg[0x105]=0x0
    Reg[0x106]=0xa
    Reg[0x107]=0x3
    Reg[0x108]=0x1
    Reg[0x109]=0x0
    Reg[0x10a]=0x2
    Reg[0x10b]=0x0
    Reg[0x200]=0xe6
    Reg[0x201]=0x4
    Reg[0x202]=0x3
    Reg[0x203]=0x1
    Reg[0x204]=0x4
    Reg[0x205]=0x2a
    Reg[0x206]=0x0
    Reg[0x207]=0x1
    Reg[0x208]=0x3
    Reg[0x209]=0x0
    Reg[0x300]=0x40
    Reg[0x301]=0x0
    Reg[0x302]=0x1f
    Reg[0x32a]=0x0
    Reg[0x32b]=0x0
    Reg[0x32c]=0x0
    Reg[0x32d]=0x0
    Reg[0x32e]=0x0
    Reg[0x400]=0xe0
    Reg[0x401]=0x1
    Reg[0x402]=0x0
    Reg[0x403]=0x80
    Reg[0x404]=0x4
    Reg[0x500]=0x10
    Reg[0x501]=0xd4
    Reg[0x502]=0x7
    Reg[0x503]=0xff
    Reg[0x504]=0xff
    Reg[0x505]=0x7
    Reg[0x506]=0x3
    Reg[0x507]=0xc
    Reg[0x508]=0xf2
    Reg[0x509]=0x8
    

  • HI,

    please attach the stp file you used with the AD9528 eval software to create the configuration. For some reason, I saved the dump lines you attached in to a file and I get an error when I load it.

    Then please also send me the ADIsimCLK file you created to simulate the configuration.

    Thanks

    Petre

Reply
  • HI,

    please attach the stp file you used with the AD9528 eval software to create the configuration. For some reason, I saved the dump lines you attached in to a file and I get an error when I load it.

    Then please also send me the ADIsimCLK file you created to simulate the configuration.

    Thanks

    Petre

Children
  • Hi Sir Petre,

    I used above register setting and deduced value to configure ADIsimCLK. Although, I was not able to configure it correctly and we don't have working stp file. I've dumped the register again from the board. Please check configuration in attachment. 

    Regards,

    MKS

    .

    -------------------------------------------------------------------------------------------------------------------
    refA_Frequency_Hz = 0
    refA_bufferCtrl = 4 ----------------------> Disabled 
    
    refB_Frequency_Hz = 0
    refB_Divider = 1  ------------------------> R Divider
    refB_bufferCtrl = 4
    
    vcxo_Frequency_Hz = 245760000
    vcxoBufferCtrl = 1
    
    refA_Divider = 1  ------------------------> R Divider
    nDividerPll1 = 1 -------------------------> N Divider
    
    PLL2
    -------
    
    rfDivider = 4 (M Divider)
    n2Divider = 4
    r1Divider = 1 
    totalNdiv = 16
    
    Sysref
    --------
    sysrefRequestMethod = 0 ------------------------> SPI
    sysrefSource = 2 -------------------------------> Internal
    sysrefPinEdgeMode = 0---------------------------> Lvl Active high
    sysrefPinBufferMode = 4 ------------------------> Disabled ( issue in code)
    sysrefPatternMode = 0 -------------------------- N Shot Pulse
    sysrefDivide = 480  ; // K-divider
    sysrefNshotMode =  1 Pulse
    ----------------------------------------------------------------------------------------------------------------------
    
    
    Register Dump
    ===============
    
    Reg[0]=0x3c
    Reg[1]=0x0
    Reg[0x100]=0x1
    Reg[0x101]=0x0
    Reg[0x102]=0x1
    Reg[0x103]=0x0
    Reg[0x104]=0x0
    Reg[0x105]=0x0
    Reg[0x106]=0xa
    Reg[0x107]=0x3
    Reg[0x108]=0x1
    Reg[0x109]=0x0
    Reg[0x10a]=0x2
    Reg[0x10b]=0x0
    Reg[0x200]=0xe6
    Reg[0x201]=0x4
    Reg[0x202]=0x3
    Reg[0x203]=0x1
    Reg[0x204]=0x4
    Reg[0x205]=0x2a
    Reg[0x206]=0x0
    Reg[0x207]=0x1
    Reg[0x208]=0x3
    Reg[0x209]=0x0
    Reg[0x300]=0x40
    Reg[0x301]=0x0
    Reg[0x302]=0x1f
    Reg[0x32a]=0x0
    Reg[0x32b]=0x0
    Reg[0x32c]=0x0
    Reg[0x32d]=0x0
    Reg[0x32e]=0x0
    Reg[0x400]=0xe0
    Reg[0x401]=0x1
    Reg[0x402]=0x0
    Reg[0x403]=0x80
    Reg[0x404]=0x4
    Reg[0x500]=0x10
    Reg[0x501]=0xd4
    Reg[0x502]=0x7
    Reg[0x503]=0xff
    Reg[0x504]=0xff
    Reg[0x505]=0x7
    Reg[0x506]=0x3
    Reg[0x507]=0xc
    Reg[0x508]=0xf2
    Reg[0x509]=0x8
    

  • Hi,

    I replicated the AD9528 eval software image you provided and I have certain settings that are different than yours. I, for example, use the PLL2 charge pump current at its max current, 893.5uA. You use a lower value, 805 uA. This means a lower PLL2 loop bandwidth, which may be what you in the end wanted.

    You do not have the registers 0x303 to 0x329 set. These are registers that manage the outputs, so definitely what you have on your AD9528 eval software figure does not match the register values.

    Anyway, please find attached the stp file I created based on your figure and the ADIsimCLK file I created based on these settings. Please use this file to see the behavior of the AD9528. Take out the txt extension before using them.

    I recommend making changes first in the eval software, see if they are accepted and then introduce them into the ADIsimCLK to study their effects.

    AD9528_setup2.clk.txt

    <header>
    product = AD9528
    softwareversion = 1.0.0.3
    </header>
    
    <detailed setup information>
    -- PLL1 --
     - Ref A -
        Powered Down
     - Ref B -
        Powered Down
     - Clk In -
        Osc Freq: 245.76 MHz
        N1: 1
        PFD Freq: 245.76 MHz
    ------------------
    -- PLL2 --
        Input Freq: 245.76 MHz
        R2: /1
        PFD Freq: 245.76 MHz
        N2: 4
        Dist Freq: 983.04 MHz
        M: 4
        VCO Freq: 3.93216 GHz
    ----------------------
    -- SysRef --
        Source: Internal Generation
        Freq: 512.0 kHz
    ----------------------
    -- Distribution --
        Input Source: PLL2
        Input Freq: 983.04 MHz
     - Out 0 -
        Input Source: Sysref
        Output Freq: 512.0 kHz
     - Out 1 -
        Input Source: D1
        D1:4
        Output Freq: 245.76 MHz
     - Out 2 -
        Input Source: D2
        D2:4
        Output Freq: 245.76 MHz
     - Out 3 -
        Input Source: D3
        D3:4
        Output Freq: 245.76 MHz
     - Out 4 -
        Input Source: D4
        D4:5
        Output Freq: 196.608 MHz
     - Out 5 -
        Input Source: Sysref
        Output Freq: 512.0 kHz
     - Out 6 -
        Input Source: D6
        D6:5
        Output Freq: 196.608 MHz
     - Out 7 -
        Input Source: Sysref
        Output Freq: 512.0 kHz
     - Out 8 -
        Input Source: D8
        D8:5
        Output Freq: 196.608 MHz
     - Out 9 -
        Input Source: Sysref
        Output Freq: 512.0 kHz
     - Out 10 -
        Input Source: D10
        D10:5
        Output Freq: 196.608 MHz
     - Out 11 -
        Input Source: Sysref
        Output Freq: 512.0 kHz
     - Out 12 -
        Input Source: PLL1
        Output Freq: 245.76 MHz
     - Out 13 -
        Input Source: PLL1
        Output Freq: 245.76 MHz
    ----------------------
    </detailed setup information>
    
    <registers>
    Register (Hex),	Value (Hex),	Value (Dec)
    0x0,		0x00,		0
    0x1,		0x00,		0
    0x3,		0x05,		5
    0x4,		0xFF,		255
    0x5,		0x00,		0
    0x6,		0x03,		3
    0xa,		0x00,		0
    0xb,		0x00,		0
    0xc,		0x56,		86
    0xd,		0x04,		4
    0xf,		0x00,		0
    0x100,		0x01,		1
    0x101,		0x00,		0
    0x102,		0x01,		1
    0x103,		0x00,		0
    0x104,		0x01,		1
    0x105,		0x00,		0
    0x106,		0x0C,		12
    0x107,		0x00,		0
    0x108,		0x00,		0
    0x109,		0x00,		0
    0x10a,		0x00,		0
    0x10b,		0x00,		0
    0x200,		0xFF,		255
    0x201,		0x04,		4
    0x202,		0x03,		3
    0x203,		0x00,		0
    0x204,		0x04,		4
    0x205,		0x2A,		42
    0x206,		0x00,		0
    0x207,		0x00,		0
    0x208,		0x03,		3
    0x209,		0x00,		0
    0x300,		0x40,		64
    0x301,		0x00,		0
    0x302,		0x04,		4
    0x303,		0x00,		0
    0x304,		0x00,		0
    0x305,		0x03,		3
    0x306,		0x00,		0
    0x307,		0x00,		0
    0x308,		0x03,		3
    0x309,		0x00,		0
    0x30a,		0x00,		0
    0x30b,		0x03,		3
    0x30c,		0x00,		0
    0x30d,		0x00,		0
    0x30e,		0x04,		4
    0x30f,		0x40,		64
    0x310,		0x00,		0
    0x311,		0x00,		0
    0x312,		0x00,		0
    0x313,		0x00,		0
    0x314,		0x04,		4
    0x315,		0x40,		64
    0x316,		0x00,		0
    0x317,		0x00,		0
    0x318,		0x00,		0
    0x319,		0x00,		0
    0x31a,		0x04,		4
    0x31b,		0x40,		64
    0x31c,		0x00,		0
    0x31d,		0x00,		0
    0x31e,		0x00,		0
    0x31f,		0x00,		0
    0x320,		0x04,		4
    0x321,		0x40,		64
    0x322,		0x00,		0
    0x323,		0x00,		0
    0x324,		0x20,		32
    0x325,		0x00,		0
    0x326,		0x00,		0
    0x327,		0x20,		32
    0x328,		0x00,		0
    0x329,		0x00,		0
    0x32a,		0x00,		0
    0x32b,		0x00,		0
    0x32c,		0x00,		0
    0x32d,		0x00,		0
    0x32e,		0x00,		0
    0x400,		0xF0,		240
    0x401,		0x00,		0
    0x402,		0x18,		24
    0x403,		0x91,		145
    0x404,		0x04,		4
    0x500,		0x10,		16
    0x501,		0x00,		0
    0x502,		0x00,		0
    0x503,		0xFF,		255
    0x504,		0xFF,		255
    0x505,		0x00,		0
    0x506,		0x00,		0
    0x507,		0x00,		0
    0x508,		0x00,		0
    0x509,		0x00,		0
    </registers>
    
    <frequencies>
    50000000;122880000;245760000;768000
    </frequencies>
    

    Petre

  • Hi Sir Petre,

    Thanks so much for unleashing AD9528 for beginners and telling us about the area to start with. I really thank you to spend your valuable time to comment on my post. You've shared very informative thing which will certainly help me and many others to deep dive into AD9528. 

    Thanks so much Sir Petre.

    Sincere Regards,

    MKS