Hi Team ADI,
I am working on AD9528 and I am giving reference from AD9545 to AD9528 VCXO.
-> AD9545 PLLs are locked as expected
-> AD9528 PLL2 is locked as expected but PLL1 is not locked because of N1 divider. If I make N1 = 8 then PLL1 gets lock.
I've few queries on this. Could you please clarify this ?
1) Does it really matter that PLL1 must be locked ?
2) What will be the impact when I choose different value for out-div and N2 i.e. (N2 = out-div) ?
3) For reduction of high in-band noise, input frequency to PLL1/PLL2 (PFD) must be higher that mean to me "N1 and N2 divider
must have greater value". Is it true ?
[edited by: MKS3134 at 8:27 AM (GMT -4) on 22 Jul 2022]