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ADF4372 SCLK Falling Edge to Data Out (Muxout) Valid Delay (Taccess)

Category: Hardware
Product Number: ADF4372

Hi, 

The ADF4372 datasheet (https://www.analog.com/media/en/technical-documentation/data-sheets/adf4372.pdf) specifies a SCLK Falling Edge to SDIO Valid Propagation Delay, Taccess, of 10ns. This number is listed in the "Min' column and there are no other specifications provided for this timing characteristic as shown in below image. 

A few questions on this:

1. Can it be confirmed this specification applies to register readback data sent out on the MUXOUT pin when in 4 wire SPI mode just as it would apply to data sent out on the SDIO pin in 3 wire SPI mode?

2. Can it be confirmed what the min/max range of this delay is? Is 10ns really the minimum with no upper bound, or is 10ns typical and would expect min/max to be within some small bound of this value (for example 9ns min, 11ns max). 

3. How can it be rectified that the part is rated for 50MHz SPI operation while the SCLK falling edge to Data out delay is 10ns? At 50MHz, the clock period is 20ns. Standard SPI protocol would dictate that the data readback (MISO) is clocked in by the controller on the rising edge of the SPI clock. If data is clocked out of the ADF4372 (peripheral) on the falling edge of SCLK, it would have to propagate back to the controller within 10ns (minus controller's required setup time to rising edge of clock) to be clocked into controller on rising edge of clock. This timing would not work out at such a high clock rate. 

Does ADI have a specific recommendation for SPI settings to use for register readback operation at high SPI clock frequencies?

Thanks!