Post Go back to editing

AD9545 unable to lock 1pps all the time

Category: Hardware
Product Number: AD9545

Hello,

       The current application scenario is that the refaa of ad9545 inputs 1PPS signal, the outputs of pll0 and PLL1 track 1PPS signal, and OCXO crystal oscillator is connected to M0 pin for clock compensation. OCXO's accuracy is 10 ppb.

      The current problem is that the locking status of the clocks pll0 and PLL1 is unstable. When pll0 is unstable, read the status of the 0x3100 register with a value of 0x2a, indicating that the frequency of dpll0 is not locked. Read the status of the refaa of 0x3006 with a value of 0x10, indicating that the refaa is valid. When PLL1 locking is unstable, read the status of 0x3200 register, the value is 0x2c, indicating that the phase of dpll1 is not locked. Read the status of 0x3006 refaa, which is 0x10, indicating that refaa is valid.

    Please help to see where there may be problems. The attachment is the current configuration file. Thank you for your support!

AD9545_0609.zip

  • Hi,

    the AD9545 configuration seems correct.

    You should also monitor the register 0x3002 (execute IO Update before reading it because it is a buffered register), bits 2 and 1. They should tell you if the AuxDPLL is locked or not (bit 1) and if the reference clock to the AuxDPLL (the one you apply at M0 pin) is faulty or not.

    You need the AuxDPLL to be locked in order for the DPLLs to lock onto REFAA=1Hz with a 50mHz bandwidth.

    If the AuxDPLL is locked and you still get unlock periods, then you should look at the 1Hz clock you give at REFAA. Please use a rubidium or a cesium based signal generator to obtain a 1 Hz clock. Make the AD9545 to fully lock and then you can move to using a GPS module.

     I already gave you the same advice in this issue:  AD9545 1pps ref clock can't phase lock 

    Please read it again because I do not have anything different to recommend.

    Petre