We are using AD9523-1 as clocking source for our ADC system, working along with AD9680 and Xilinx Zynq, with a similar design as FMCDAQ2 provided by ADI.
We are now testing our board, but it seems that the clocking chip cannot power up its PLL2 component. Once we write "1" to bit 1 at register 0x233 and then write 0x01 to register 0x234, the chip fails, and all the registers get restored to default state, all our settings get lost, and register 0x233 still reads 0x07.
We also tried writing 0x05 to register 0x233 (without powering up PLL2), and the readback from the chip is nonetheless correct, and status VCXO is OK (bit 5 of register 0x22c reads 1). We also tried to disable (tristate) all the outputs before powering up PLL2, but the chip still fails.
The software code is simply adapted from ADI's NO-OS driver, and the SPI bus as well as the oscillator (125 MHz, differential LVDS) works correctly.
Attached you can find the schematic of our design and the register configuration. We appreciate your timely assistance.
Added description of register configuration
[edited by: torwa at 5:27 AM (GMT -4) on 16 May 2022]