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AD9528 Clock Output

Category: Hardware

I am using AD9528 chips to generate device clocks and Sysref for AD9375 which are as follows:

Reference clock used is 10MHz and VCXO clock is 122.88MHz 

Required Outputs - 122.88MHz (Device Clock) & Sysref - 0.96MHz

As per Evaluation software, all PLLs are getting Locked

But in my board, Eventhough PLLs are not getting Locked. I am able to see the output frequency of both device clocks and Sysref. But the voltage levels are not in recommended limits.

Device Clock voltage level - 150mV after AC cap (near to AD9375 Pin)

1. Sysref Clock( Retimed by PLL1 Output) - Unable to see clock

2. Sysref Clock -  Output frequency is there. but voltage standard is in cmos level. (Peak to Peak Voltage is 1.8V)

Issues:

1. Reasons for PLLs not getting Locked

 2. Voltage Level of Sysref is misguiding

 3. What is resample Sysref

The register values are as follows:

Register (PLL1) Values Register(PLL2) Values Values (O/P channel) Sysref(retimed by PLL1 Output)
0100 7D 0200   Device Clock Able to get device clock, But peak -peak is not as expected 60 Unable to get Sysref
0101 00 0201 04 20 00
0102 7D 0202 03 00 09
0103 00 0203 10 09
0104 40 0204 04 Register (Sysref Settings) Values
0105 00 0205 2A 0400 40
0106 0A 0206 00 0401 00
0107 03 0207 18 0402 18
0108 18 0208 C3 0403 9A
0109 00 0209 00 0404 4
010A 02
010B 00
 
Power Down Control  Default Values  
  • HI,

    not clear to me what you mean when you say "As per Evaluation software, all PLLs are getting Locked". Did you try the configuration on an AD9528 evaluation board?

    In the future, please just attach the stp file you create with the evaluation software. It makes things much easier to look at.

    Introducing the register values you sent, it does not seem you are able to create a 122.88MHz output clock.

    There is no integer divider that can divide the VCO value you use (122.88E6/24*196*4)  to obtain a 122.88MHz output.

    Because the 122.88MHz output clock is not phase aligned to the 10MHz reference clock, using the 10MHz reference clock is not necessary. I recommend to create the 122.88MHz output directly using the PLL2 and the VCXO and power down PLL1.

    I configured the PLL2 in this sense. Attached is the related stp file (please take out the txt extension before loading it onto the evaluation software). I set OUT0 at 122.88MHz and OUT1=SYSREF. Configure yourself the right drivers for these outputs and the other outputs.

    <header>
    product = AD9528
    softwareversion = 1.0.0.3
    </header>
    
    <detailed setup information>
    -- PLL1 --
     - Ref A -
        Powered Down
     - Ref B -
        Powered Down
     - Clk In -
        Osc Freq: 122.88 MHz
        N1: 64
        PFD Freq: 1.92 MHz
    ------------------
    -- PLL2 --
        Input Freq: 122.88 MHz
        R2: /1
        PFD Freq: 122.88 MHz
        N2: 8
        Dist Freq: 983.04 MHz
        M: 4
        VCO Freq: 3.93216 GHz
    ----------------------
    -- SysRef --
        Source: Internal Generation
        Freq: 960.0 kHz
    ----------------------
    -- Distribution --
        Input Source: PLL2
        Input Freq: 983.04 MHz
     - Out 0 -
        Input Source: D0
        D0:8
        Output Freq: 122.88 MHz
     - Out 1 -
        Input Source: Sysref
        Output Freq: 960.0 kHz
     - Out 2 -
        Input Source: D2
        D2:5
        Output Freq: 196.608 MHz
     - Out 3 -
        Input Source: Sysref
        Output Freq: 960.0 kHz
     - Out 4 -
        Input Source: D4
        D4:5
        Output Freq: 196.608 MHz
     - Out 5 -
        Input Source: Sysref
        Output Freq: 960.0 kHz
     - Out 6 -
        Input Source: D6
        D6:5
        Output Freq: 196.608 MHz
     - Out 7 -
        Input Source: Sysref
        Output Freq: 960.0 kHz
     - Out 8 -
        Input Source: D8
        D8:5
        Output Freq: 196.608 MHz
     - Out 9 -
        Input Source: Sysref
        Output Freq: 960.0 kHz
     - Out 10 -
        Input Source: D10
        D10:5
        Output Freq: 196.608 MHz
     - Out 11 -
        Input Source: Sysref
        Output Freq: 960.0 kHz
     - Out 12 -
        Input Source: PLL1
        Output Freq: 122.88 MHz
     - Out 13 -
        Input Source: PLL1
        Output Freq: 122.88 MHz
    ----------------------
    </detailed setup information>
    
    <registers>
    Register (Hex),	Value (Hex),	Value (Dec)
    0x0,		0x00,		0
    0x1,		0x00,		0
    0x3,		0x05,		5
    0x4,		0xFF,		255
    0x5,		0x00,		0
    0x6,		0x03,		3
    0xa,		0x00,		0
    0xb,		0x00,		0
    0xc,		0x56,		86
    0xd,		0x04,		4
    0xf,		0x00,		0
    0x100,		0x7D,		125
    0x101,		0x00,		0
    0x102,		0x7D,		125
    0x103,		0x00,		0
    0x104,		0x40,		64
    0x105,		0x00,		0
    0x106,		0x0A,		10
    0x107,		0x03,		3
    0x108,		0x18,		24
    0x109,		0x00,		0
    0x10a,		0x02,		2
    0x10b,		0x00,		0
    0x200,		0xFF,		255
    0x201,		0x08,		8
    0x202,		0x03,		3
    0x203,		0x00,		0
    0x204,		0x04,		4
    0x205,		0x2A,		42
    0x206,		0x00,		0
    0x207,		0x18,		24
    0x208,		0x07,		7
    0x209,		0x00,		0
    0x300,		0x00,		0
    0x301,		0x00,		0
    0x302,		0x07,		7
    0x303,		0x40,		64
    0x304,		0x00,		0
    0x305,		0x07,		7
    0x306,		0x00,		0
    0x307,		0x00,		0
    0x308,		0x04,		4
    0x309,		0x40,		64
    0x30a,		0x00,		0
    0x30b,		0x00,		0
    0x30c,		0x00,		0
    0x30d,		0x00,		0
    0x30e,		0x04,		4
    0x30f,		0x40,		64
    0x310,		0x00,		0
    0x311,		0x00,		0
    0x312,		0x00,		0
    0x313,		0x00,		0
    0x314,		0x04,		4
    0x315,		0x40,		64
    0x316,		0x00,		0
    0x317,		0x00,		0
    0x318,		0x00,		0
    0x319,		0x00,		0
    0x31a,		0x04,		4
    0x31b,		0x40,		64
    0x31c,		0x00,		0
    0x31d,		0x00,		0
    0x31e,		0x00,		0
    0x31f,		0x00,		0
    0x320,		0x04,		4
    0x321,		0x40,		64
    0x322,		0x00,		0
    0x323,		0x00,		0
    0x324,		0x20,		32
    0x325,		0x00,		0
    0x326,		0x00,		0
    0x327,		0x20,		32
    0x328,		0x00,		0
    0x329,		0x00,		0
    0x32a,		0x00,		0
    0x32b,		0x00,		0
    0x32c,		0x00,		0
    0x32d,		0x00,		0
    0x32e,		0x00,		0
    0x400,		0x40,		64
    0x401,		0x00,		0
    0x402,		0x00,		0
    0x403,		0x80,		128
    0x404,		0x04,		4
    0x500,		0x14,		20
    0x501,		0x00,		0
    0x502,		0x00,		0
    0x503,		0xFF,		255
    0x504,		0xFF,		255
    0x505,		0x00,		0
    0x506,		0x00,		0
    0x507,		0x00,		0
    0x508,		0x00,		0
    0x509,		0x00,		0
    </registers>
    
    <frequencies>
    10000000;10000000;122880000;1
    </frequencies>
    

    Petre