I am using AD9528 chips to generate device clocks and Sysref for AD9375 which are as follows:
Reference clock used is 10MHz and VCXO clock is 122.88MHz
Required Outputs - 122.88MHz (Device Clock) & Sysref - 0.96MHz
As per Evaluation software, all PLLs are getting Locked
But in my board, Eventhough PLLs are not getting Locked. I am able to see the output frequency of both device clocks and Sysref. But the voltage levels are not in recommended limits.
Device Clock voltage level - 150mV after AC cap (near to AD9375 Pin)
1. Sysref Clock( Retimed by PLL1 Output) - Unable to see clock
2. Sysref Clock - Output frequency is there. but voltage standard is in cmos level. (Peak to Peak Voltage is 1.8V)
Issues:
1. Reasons for PLLs not getting Locked
2. Voltage Level of Sysref is misguiding
3. What is resample Sysref
The register values are as follows:
| Register (PLL1) | Values | Register(PLL2) | Values | Values (O/P channel) | Sysref(retimed by PLL1 Output) | |||||
| 0100 | 7D | 0200 | Device Clock | Able to get device clock, But peak -peak is not as expected | 60 | Unable to get Sysref | ||||
| 0101 | 00 | 0201 | 04 | 20 | 00 | |||||
| 0102 | 7D | 0202 | 03 | 00 | 09 | |||||
| 0103 | 00 | 0203 | 10 | 09 | ||||||
| 0104 | 40 | 0204 | 04 | Register (Sysref Settings) | Values | |||||
| 0105 | 00 | 0205 | 2A | 0400 | 40 | |||||
| 0106 | 0A | 0206 | 00 | 0401 | 00 | |||||
| 0107 | 03 | 0207 | 18 | 0402 | 18 | |||||
| 0108 | 18 | 0208 | C3 | 0403 | 9A | |||||
| 0109 | 00 | 0209 | 00 | 0404 | 4 | |||||
| 010A | 02 | |||||||||
| 010B | 00 | |||||||||
| Power Down Control | Default Values | |||||||||
