I want to use AD9518-3 as an excel sheet in the attached file.
If you could change the value of R and fix other counter values (P,B,A,N,R/B) to change the value of Fout to 22.222MHz~25M (cycle 45ns~40ns) and change the clock through SPI control. do.
Please review whether it is possible.
thank you.
Hi,
I see you did not like the AD9543 based solution I proposed in your other post:
RE: AD9544 Question on how to calculate output clock based on input clock frequency
The advantage of this solution is that you can change the output clock frequency continuously, without the output clock having a phase jump. In addition, the phase noise of the output is better than the phase noise of an AD9518 output.
You seem now to want to change the output frequency by changing the parameters of a PLL. You may need to recalibrate the VCO every time you change the parameters and I am pretty sure you will need to execute also a sync command. This sync operation alone will stop the clock generation for a period of time, which means a big phase jump will happen every time you change the PLL parameters:
I attach a python 3.9 script (take out the txt extension) in which you can introduce the desired reference and output frequencies and calculate the AD9518-3 PLL loop parameters you need. If the script finds multiple solutions, choose the one with the lower feedback divider. I also recommend introducing the values into the AD9518-3 evaluation software (it works without an evaluation board), so the software can calculate the P, A and B values of the PLL feedback divider. There may be cases in which no solution may be found for a particular feedback divider value.
# -*- coding: utf-8 -*-
"""
Created on Tue Jan 25 10:34:57 2022
This script calculates the AD9518-3 parameters.
The procedure:
- Introduce REFfrequency in Hz
- Introduce PLL created OUT0 (i.e. OUT0 of the AD9518), OUT1 (i.e.OUT2 of the AD9518),
OUT2 (i.e. OUT4 of the AD9518) frequencies in Hz
- Set unused outputs outputs to 1 (that is 1 Hz)
- the script will compute the parameters of PLL block
@author: PMinciu
"""
import sys, struct
import xml.etree.ElementTree as ET
from math import gcd, ceil, lcm, floor
from fractions import Fraction
from bitarray import bitarray as BitArray
import os
#Introduce the reference clock REF frequency in Hz
REF=25E6
#Introduce the output frequencies in Hz. Introduce only the outputs created by PLL2
#If an output is not used, introduce it as 1Hz
OUT0=25E6
OUT1=1
OUT2=1
#create an array of the outputs
OUT=[OUT0, OUT1, OUT2]
#calculate the least common multiple of the outputs
common_out=lcm(int(OUT0), int(OUT1), int(OUT2))
#The PLL VCO frequency range is 1.75GHz to 2.05GHz
#Calculate the integer Dividers between VCOmin/common_out and VCOmax/common_out
VCO_Div=[]
for i in range(ceil(1.75E9/common_out), floor(2.05E9/common_out)+1):
VCO_Div.append(i)
M1=[2, 3, 4, 5, 6]
Doubler=[1]
PLL_VCO=0
#we make a loop that goes through all the VCO_Div integers
for i in range(0, len(VCO_Div)):
#make a look that goes through all M1 values: 2, 3, 4, 5, 6
for j in range(0, len(M1)):
#continue only if M1 is a divisor of VCO_Div
# if (VCO_Div[i] % M1[j] ==0):
#calculate the PLL2 VCO frequency
PLL_VCO=VCO_Div[i]*common_out
#see if the doubler can be used
for ii in range(0, len(Doubler)):
N2_over_R1=PLL_VCO/Doubler[ii]/REF
#calculate the numerator and denominator of N2_over_R1
#for 2/3 like fractions, limit the denominator to 1000
a=Fraction(N2_over_R1).limit_denominator(1000)
R1=a.denominator
N2=a.numerator
if ((R1>16383) | (N2>262175)):
print("PLL Cannot be configured because R1>16383 or N2>262175: ","R1=", R1, ", N2=", N2, sep='')
else:
#calculate all the output dividers for the output that are not 1
for k in range(0, len(OUT)):
if (OUT[k] != 1):
if ((Doubler[ii]*REF*N2/R1/M1[j]) % OUT[k]==0):
Out_Div=Doubler[ii]*REF*N2/R1/M1[j]/OUT[k]
if Out_Div<=32:
print("PLL Components: VCO=", PLL_VCO, ", R1=", R1,
", Doubler=", Doubler[ii], ", N2=", N2,sep='')
print(" OUT",k," divider is:",
int(Out_Div), ", M1=", M1[j], sep='')
# else:
# print("PLL cannot be configured because Out_Div is not an integer number")
#if PLL_VCO remains 0 after this loop, it signifies the PLL configuration
#does not have a solution
if (PLL_VCO==0):
print("PLL cannot be configured for the desired outputs")
"""
#The prime factors lower than 55 are
pf=[2,3,5,7,11,13,17,19,23,29,31,37,41,43,47]
#initialize the powers of each prime factor
pf_power=[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
x = initial_PFD
for i in range(len(pf)):
while((x % pf[i])==0):
pf_power[i]+=1 #increase the power of the prime number that is a factor of x
x = x/pf[i]
print("The prime factorization of the greater common divisor of REFA and VCXO is")
for i in range (len(pf)):
print(pf[i], pf_power[i])
"""
I was able to obtain solutions for REF=25MHz and 25MHz and 22.222Mhz outputs (different configurations for each case, of course)
Petre
Hi,
I see you did not like the AD9543 based solution I proposed in your other post:
RE: AD9544 Question on how to calculate output clock based on input clock frequency
The advantage of this solution is that you can change the output clock frequency continuously, without the output clock having a phase jump. In addition, the phase noise of the output is better than the phase noise of an AD9518 output.
You seem now to want to change the output frequency by changing the parameters of a PLL. You may need to recalibrate the VCO every time you change the parameters and I am pretty sure you will need to execute also a sync command. This sync operation alone will stop the clock generation for a period of time, which means a big phase jump will happen every time you change the PLL parameters:
I attach a python 3.9 script (take out the txt extension) in which you can introduce the desired reference and output frequencies and calculate the AD9518-3 PLL loop parameters you need. If the script finds multiple solutions, choose the one with the lower feedback divider. I also recommend introducing the values into the AD9518-3 evaluation software (it works without an evaluation board), so the software can calculate the P, A and B values of the PLL feedback divider. There may be cases in which no solution may be found for a particular feedback divider value.
# -*- coding: utf-8 -*-
"""
Created on Tue Jan 25 10:34:57 2022
This script calculates the AD9518-3 parameters.
The procedure:
- Introduce REFfrequency in Hz
- Introduce PLL created OUT0 (i.e. OUT0 of the AD9518), OUT1 (i.e.OUT2 of the AD9518),
OUT2 (i.e. OUT4 of the AD9518) frequencies in Hz
- Set unused outputs outputs to 1 (that is 1 Hz)
- the script will compute the parameters of PLL block
@author: PMinciu
"""
import sys, struct
import xml.etree.ElementTree as ET
from math import gcd, ceil, lcm, floor
from fractions import Fraction
from bitarray import bitarray as BitArray
import os
#Introduce the reference clock REF frequency in Hz
REF=25E6
#Introduce the output frequencies in Hz. Introduce only the outputs created by PLL2
#If an output is not used, introduce it as 1Hz
OUT0=25E6
OUT1=1
OUT2=1
#create an array of the outputs
OUT=[OUT0, OUT1, OUT2]
#calculate the least common multiple of the outputs
common_out=lcm(int(OUT0), int(OUT1), int(OUT2))
#The PLL VCO frequency range is 1.75GHz to 2.05GHz
#Calculate the integer Dividers between VCOmin/common_out and VCOmax/common_out
VCO_Div=[]
for i in range(ceil(1.75E9/common_out), floor(2.05E9/common_out)+1):
VCO_Div.append(i)
M1=[2, 3, 4, 5, 6]
Doubler=[1]
PLL_VCO=0
#we make a loop that goes through all the VCO_Div integers
for i in range(0, len(VCO_Div)):
#make a look that goes through all M1 values: 2, 3, 4, 5, 6
for j in range(0, len(M1)):
#continue only if M1 is a divisor of VCO_Div
# if (VCO_Div[i] % M1[j] ==0):
#calculate the PLL2 VCO frequency
PLL_VCO=VCO_Div[i]*common_out
#see if the doubler can be used
for ii in range(0, len(Doubler)):
N2_over_R1=PLL_VCO/Doubler[ii]/REF
#calculate the numerator and denominator of N2_over_R1
#for 2/3 like fractions, limit the denominator to 1000
a=Fraction(N2_over_R1).limit_denominator(1000)
R1=a.denominator
N2=a.numerator
if ((R1>16383) | (N2>262175)):
print("PLL Cannot be configured because R1>16383 or N2>262175: ","R1=", R1, ", N2=", N2, sep='')
else:
#calculate all the output dividers for the output that are not 1
for k in range(0, len(OUT)):
if (OUT[k] != 1):
if ((Doubler[ii]*REF*N2/R1/M1[j]) % OUT[k]==0):
Out_Div=Doubler[ii]*REF*N2/R1/M1[j]/OUT[k]
if Out_Div<=32:
print("PLL Components: VCO=", PLL_VCO, ", R1=", R1,
", Doubler=", Doubler[ii], ", N2=", N2,sep='')
print(" OUT",k," divider is:",
int(Out_Div), ", M1=", M1[j], sep='')
# else:
# print("PLL cannot be configured because Out_Div is not an integer number")
#if PLL_VCO remains 0 after this loop, it signifies the PLL configuration
#does not have a solution
if (PLL_VCO==0):
print("PLL cannot be configured for the desired outputs")
"""
#The prime factors lower than 55 are
pf=[2,3,5,7,11,13,17,19,23,29,31,37,41,43,47]
#initialize the powers of each prime factor
pf_power=[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
x = initial_PFD
for i in range(len(pf)):
while((x % pf[i])==0):
pf_power[i]+=1 #increase the power of the prime number that is a factor of x
x = x/pf[i]
print("The prime factorization of the greater common divisor of REFA and VCXO is")
for i in range (len(pf)):
print(pf[i], pf_power[i])
"""
I was able to obtain solutions for REF=25MHz and 25MHz and 22.222Mhz outputs (different configurations for each case, of course)
Petre