I'm trying to use the AD9544.
I want to take a REF 25MHz input and create a synchronized output 25MHz LVDS clock.
I would like to change the additional output 25MHz in steps of 5Khz to 50Khz depending on the control. (Ex. 5KHz step: ..., 24.995MHz, 25.000MHz, 25.005MHz, 25.010MHz,...)
I don't have EVB so I can't use ACE, so I guess I'll have to create the registers myself.
So I need the help below.
1) Default register setting value
2) Calculation formula to change the frequency
Help.
Thank you.
Hi,
first, the ACE works without the evaluation board being connected to the PC. You should use it to obtain the values for the AD9544 registers. The GUI contains a tab called Save Registers that when clicked, it outputs a text file with the registers and their values.
If you set the DPLL to lock onto a 25MHz clock, the DPLL will lock and you'll not be able to change the output clock frequency in steps of 5kHz to 50kHz.
I propose to use an auxiliary NCO set at for example, 50kHz and make the DPLL to lock onto it and generate 25MHz. This makes for a multiplication number of 500. If you need then to change the 25MHz by 5kHz, this means changing the frequency of the AuxNCO by 50E3*5E3/25E6=10Hz
You can also adjust the phase of the AuxNCO.
If you want the 25MHz output to be phase aligned to a 25MHz reference clock, bring one of the 25MHz outputs to an input. Time stamp the reference clock and this output clock and use the timing skew measurement to find the phase offset between them. Then introduce this phase offset with opposite sign into the DPLL Phase Offset registers shown in the figure below(always use the AD9545 rev C data sheet as reference for the AD9544 or AD9543 as these data sheets are still at rev0)
The AD9544 does not have an auxiliary NCO. I recommend using the AD9543 instead because this chip has two auxiliary NCOs. You could use one of them.
I also recommend procuring an AD9543 evaluation board and test first this approach on this board, so you get to learn the chip first, before jumping to create your own board.
I created this AD9543 cso file for you to take a look. I did only the DPLL0 setting onto the AuxNCO0=50kHz. You can then set the timing skew measurement yourself.
Petre
Hi,
first, the ACE works without the evaluation board being connected to the PC. You should use it to obtain the values for the AD9544 registers. The GUI contains a tab called Save Registers that when clicked, it outputs a text file with the registers and their values.
If you set the DPLL to lock onto a 25MHz clock, the DPLL will lock and you'll not be able to change the output clock frequency in steps of 5kHz to 50kHz.
I propose to use an auxiliary NCO set at for example, 50kHz and make the DPLL to lock onto it and generate 25MHz. This makes for a multiplication number of 500. If you need then to change the 25MHz by 5kHz, this means changing the frequency of the AuxNCO by 50E3*5E3/25E6=10Hz
You can also adjust the phase of the AuxNCO.
If you want the 25MHz output to be phase aligned to a 25MHz reference clock, bring one of the 25MHz outputs to an input. Time stamp the reference clock and this output clock and use the timing skew measurement to find the phase offset between them. Then introduce this phase offset with opposite sign into the DPLL Phase Offset registers shown in the figure below(always use the AD9545 rev C data sheet as reference for the AD9544 or AD9543 as these data sheets are still at rev0)
The AD9544 does not have an auxiliary NCO. I recommend using the AD9543 instead because this chip has two auxiliary NCOs. You could use one of them.
I also recommend procuring an AD9543 evaluation board and test first this approach on this board, so you get to learn the chip first, before jumping to create your own board.
I created this AD9543 cso file for you to take a look. I did only the DPLL0 setting onto the AuxNCO0=50kHz. You can then set the timing skew measurement yourself.
Petre
