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How to use GPO instead of 0x007D?

Dear Expert:
Recently I encountered the following problems when using HMC7043, can you help me answer the following?
1) The 0x007D register is an error, you can use GPO to check the Clock outputs phase status, but in my clock configuration file, no matter what kind of data is set by 0x0050, the status I check in VIVADO is always set to 1, this is why Woolen cloth?
2) I choose HMC7043 channel 0 and channel 1 as the DCLK and SYSREF of the FPGA respectively. The FPGA DCLK output buffer is in the form of LVDS. I use an oscilloscope to measure the differential single-ended voltage amplitude of the FPGA DCLK to be 450mV, that is, the differential voltage amplitude can reach 900mV. Much larger than the range in the spec, what can I do to improve it? If the differential voltage amplitude of 900mV does not affect the use of the FPGA, do I need to pay special attention and reduce the amplitude?

  • Hi,

    If you are using external RFSYNC and keeping the RFSYNC input at Logic-0 level, you can see that GPO will be at 0. After programming and providing pulse to RFSYNC,FSM goes from Reset state to Done state and GPO will go from Low to High. If you can probe the GPO output, you can see the transition. 

    If you are using SPI to synchronize the part, toggling the some bitfields (RFSYNC Input Buffer Enabled, RF Reseeder Enable) generating internal FSM start signal and FSM automatically goes from Reset state to Done state and GPO is transitioning from Low to High. 

    In either case, you can be sure that outputs are aligned without paying attention to the status of GPO. 

    450mV seems high and it will probably exceed the max limit of the FPGA. What are the values of Reg0x9F and Reg0xA0. Also, are you enabling the  High Performance Mode bit of the related channel? If so, you should disable it which will provide lower swing level at the output. 



  • Hi

    Thanks a lot for your help!
    The value of Reg0x9F is 4D, the value of Reg0xA0 is DF, our clock output driver is LVDS mode, the attachment is our HMC7043 configuration table, can you help us check where is the problem?

    dut.write(0x000, 0x01)
    dut.write(0x000, 0x00)
    dut.write(0x001, 0x00)
    dut.write(0x002, 0x00)
    dut.write(0x003, 0x34)
    dut.write(0x004, 0x1D)
    dut.write(0x006, 0x00)
    dut.write(0x007, 0x00)
    dut.write(0x00A, 0x0B)
    dut.write(0x00B, 0x07)
    dut.write(0x046, 0x00)
    dut.write(0x050, 0x0F)
    dut.write(0x054, 0x03)
    dut.write(0x05A, 0x04)
    dut.write(0x05B, 0x04)
    dut.write(0x05C, 0x00)
    dut.write(0x05D, 0x04)
    dut.write(0x064, 0x00)
    dut.write(0x065, 0x00)
    dut.write(0x071, 0x16)
    dut.write(0x078, 0x51)
    dut.write(0x079, 0x16)
    dut.write(0x07A, 0x30)
    dut.write(0x07D, 0x02)
    dut.write(0x091, 0x02)
    dut.write(0x098, 0x00)
    dut.write(0x099, 0x00)
    dut.write(0x09A, 0x00)
    dut.write(0x09B, 0xAA)
    dut.write(0x09C, 0xAA)
    dut.write(0x09D, 0xAA)
    dut.write(0x09E, 0xAA)
    dut.write(0x09F, 0x4D)
    dut.write(0x0A0, 0xDF)
    dut.write(0x0A1, 0x97)
    dut.write(0x0A2, 0x03)
    dut.write(0x0A3, 0x00)
    dut.write(0x0A4, 0x00)
    dut.write(0x0AD, 0x00)
    dut.write(0x0AE, 0x08)
    dut.write(0x0AF, 0x50)
    dut.write(0x0B0, 0x04)
    dut.write(0x0B1, 0x0D)
    dut.write(0x0B2, 0x00)
    dut.write(0x0B3, 0x00)
    dut.write(0x0B5, 0x00)
    dut.write(0x0B6, 0x00)
    dut.write(0x0B7, 0x00)
    dut.write(0x0B8, 0x00)
    dut.write(0x0C8, 0xF3)
    dut.write(0x0C9, 0x08)
    dut.write(0x0CA, 0x00)
    dut.write(0x0CB, 0x00)
    dut.write(0x0CC, 0x00)
    dut.write(0x0CD, 0x00)
    dut.write(0x0CE, 0x00)
    dut.write(0x0CF, 0x00)
    dut.write(0x0D0, 0x10)
    dut.write(0x0D2, 0xFD)
    dut.write(0x0D3, 0x00)
    dut.write(0x0D4, 0x04)
    dut.write(0x0D5, 0x00)
    dut.write(0x0D6, 0x00)
    dut.write(0x0D7, 0x00)
    dut.write(0x0D8, 0x00)
    dut.write(0x0D9, 0x00)
    dut.write(0x0DA, 0x10)
    dut.write(0x0DC, 0xF3)
    dut.write(0x0DD, 0x08)
    dut.write(0x0DE, 0x00)
    dut.write(0x0DF, 0x00)
    dut.write(0x0E0, 0x00)
    dut.write(0x0E1, 0x00)
    dut.write(0x0E2, 0x00)
    dut.write(0x0E3, 0x00)
    dut.write(0x0E4, 0x10)
    dut.write(0x0E6, 0xFD)
    dut.write(0x0E7, 0x00)
    dut.write(0x0E8, 0x01)
    dut.write(0x0E9, 0x00)
    dut.write(0x0EA, 0x00)
    dut.write(0x0EB, 0x00)
    dut.write(0x0EC, 0x00)
    dut.write(0x0ED, 0x00)
    dut.write(0x0EE, 0x10)
    dut.write(0x0F0, 0xF3)
    dut.write(0x0F1, 0x02)
    dut.write(0x0F2, 0x00)
    dut.write(0x0F3, 0x00)
    dut.write(0x0F4, 0x00)
    dut.write(0x0F5, 0x00)
    dut.write(0x0F6, 0x00)
    dut.write(0x0F7, 0x00)
    dut.write(0x0F8, 0x10)
    dut.write(0x0FA, 0xFD)
    dut.write(0x0FB, 0x00)
    dut.write(0x0FC, 0x04)
    dut.write(0x0FD, 0x00)
    dut.write(0x0FE, 0x00)
    dut.write(0x0FF, 0x00)
    dut.write(0x100, 0x00)
    dut.write(0x101, 0x00)
    dut.write(0x102, 0x10)
    dut.write(0x104, 0xF3)
    dut.write(0x105, 0x02)
    dut.write(0x106, 0x00)
    dut.write(0x107, 0x00)
    dut.write(0x108, 0x00)
    dut.write(0x109, 0x00)
    dut.write(0x10A, 0x00)
    dut.write(0x10B, 0x00)
    dut.write(0x10C, 0x10)
    dut.write(0x10E, 0xFD)
    dut.write(0x10F, 0x00)
    dut.write(0x110, 0x04)
    dut.write(0x111, 0x00)
    dut.write(0x112, 0x00)
    dut.write(0x113, 0x00)
    dut.write(0x114, 0x00)
    dut.write(0x115, 0x00)
    dut.write(0x116, 0x10)
    dut.write(0x118, 0xF3)
    dut.write(0x119, 0x08)
    dut.write(0x11A, 0x00)
    dut.write(0x11B, 0x00)
    dut.write(0x11C, 0x00)
    dut.write(0x11D, 0x00)
    dut.write(0x11E, 0x00)
    dut.write(0x11F, 0x00)
    dut.write(0x120, 0x10)
    dut.write(0x122, 0xF3)
    dut.write(0x123, 0x04)
    dut.write(0x124, 0x00)
    dut.write(0x125, 0x00)
    dut.write(0x126, 0x00)
    dut.write(0x127, 0x00)
    dut.write(0x128, 0x00)
    dut.write(0x129, 0x00)
    dut.write(0x12A, 0x10)
    dut.write(0x12C, 0xF3)
    dut.write(0x12D, 0x02)
    dut.write(0x12E, 0x00)
    dut.write(0x12F, 0x00)
    dut.write(0x130, 0x00)
    dut.write(0x131, 0x00)
    dut.write(0x132, 0x00)
    dut.write(0x133, 0x00)
    dut.write(0x134, 0x10)
    dut.write(0x136, 0xFD)
    dut.write(0x137, 0x00)
    dut.write(0x138, 0x02)
    dut.write(0x139, 0x00)
    dut.write(0x13A, 0x00)
    dut.write(0x13B, 0x00)
    dut.write(0x13C, 0x00)
    dut.write(0x13D, 0x00)
    dut.write(0x13E, 0x10)
    dut.write(0x140, 0xF3)
    dut.write(0x141, 0x02)
    dut.write(0x142, 0x00)
    dut.write(0x143, 0x00)
    dut.write(0x144, 0x00)
    dut.write(0x145, 0x00)
    dut.write(0x146, 0x00)
    dut.write(0x147, 0x00)
    dut.write(0x148, 0x10)
    dut.write(0x14A, 0xFD)
    dut.write(0x14B, 0x00)
    dut.write(0x14C, 0x02)
    dut.write(0x14D, 0x00)
    dut.write(0x14E, 0x00)
    dut.write(0x14F, 0x00)
    dut.write(0x150, 0x00)
    dut.write(0x151, 0x00)
    dut.write(0x152, 0x10)
    dut.write(0x001, 0x02)
    dut.write(0x001, 0x00)
    dut.write(0x001, 0x80)
    dut.write(0x001, 0x00)
    dut.write(0x001, 0x04)
    dut.write(0x001, 0x00)



  • Can you try to set 0x0C8=0x73?


  • Thank you again for your reply!

    I tried to set 0x0C8=0x73, it does improve the amplitude.

    I have been encountering the following problem, which is the synchronization of multipule HMC7043 chips. I hope you can help to answer it:
    RFSYNC signals for HMC7043 are one pulse and exactly same phase. RFSYNC and CLKIN signals are provided by a eval board. However, the SYSREF signals generated by RFSYNC, from different slave HMC7043 have unfixed phase difference, which is between 5ns and 200ns.

    The 0x0091 is 0x02 and the waveform of SYSREF seems right. The configuration has been shown as before reply.

    What can I do to keep the phase difference fixed at a value?