Recently I encountered the following problems when using HMC7043, can you help me answer the following?
1) The 0x007D register is an error, you can use GPO to check the Clock outputs phase status, but in my clock configuration file, no matter what kind of data is set by 0x0050, the status I check in VIVADO is always set to 1, this is why Woolen cloth?
2) I choose HMC7043 channel 0 and channel 1 as the DCLK and SYSREF of the FPGA respectively. The FPGA DCLK output buffer is in the form of LVDS. I use an oscilloscope to measure the differential single-ended voltage amplitude of the FPGA DCLK to be 450mV, that is, the differential voltage amplitude can reach 900mV. Much larger than the range in the spec, what can I do to improve it? If the differential voltage amplitude of 900mV does not affect the use of the FPGA, do I need to pay special attention and reduce the amplitude?