We have designed a board with two level HMC7043 tree, the structure is as the following figure.
ALL 7043 is set to single pulse mode. The input of RFSYNC of all Chips is single pulse with dc couple. Afiter init all the 7043, we can trigger the input RFSYNC of A, and then trace the sclk output of B1 and B2 with scope.
We have manufactured 8 boards, 5 boards' sclk from B1/B2 are in phase. There is 5ns (one cycle period)differ on the other 3 board's output(between B1 B2).
If I added 1 coarse digital delay to the sclk1/sclk3 of chip A, the phase differ did not change.
If I add 0 ddelay to chip sclk1 and 3 ddelay to sclk3 (one cycle period), the sclk outputs are in phase. It seems the input rfsync of B1/B2 is not in phase, but I trace the input RFSYNC of B1 and B2 with scope，they are in phase.
What is the reason for the differenc? Can you tell me how to debug the problem? Thanks a lot!