AD9545 1pps ref clock can't phase lock

Hi,

do you have your own board or do you use the AD9545 evaluation board?

Some things to pay attention to:

- you say DPLL1 locked in frequency, so this means the REFAA=1Hz was considered valid by the AD9545. The REFAA validation timer is the 10 ms default. I recommend increasing it to 1000ms=1s. This is the time the chip requires the reference to be in an  unfaulted state before becoming valid.

- I recommend looking at your application and see what is the phase lock specification. The default now is 700ps phase error at DPD level. I use the phase lock threshold at 2000 ps=2ns. This will make the phase lock to be declared sooner. I also like to increase the freq/phase lock fill rates to 100 from the default value of 10. This also fastens the frequency and phase lock declarations. 

- You use a OCXO(?) at M0 pin to stabilize the system clock. I do not believe the auxiliary DPLL locked because you set the 10MHz clock divider to 1 (default). It should be set to 50 because the TDCs work at 200kHz max, so we need to divide 10MHz down to 200kHz for the AuxDPLL to work. This I believe is what is really missing in your configuration.

- OUT1A is set to single ended dual divider, but the second divider at OUT1AA is 0: I recommend setting it whatever value you need.

Please note that the AD9545 evaluation board has all the outputs ac coupled, so OUT1B=1Hz will be distorted. Please connect TP307 to TP308 (that is to put VOUT_COMMON to ground as it was left floating).

AD9545_0303b.zip

I attach the cso file containing the M0 divider to 50. The system clock compensation was otherwise set correctly.

I'll let you change the rest.

Petre

Hi, Petre,

     Thanks for your reply！This is our own board,REFAA is 1pps signal from GPS，M0 pin is 10MHz OCXO（its frequency stability is ±10ppb ）for compensating system clock, OUT1A and OUT1B should be synchronize with REFAA.

 I have changed the cso configuration according to your suggestion, but OUT1A is not in phase with REFAA. The state register 0x3200 is 0x2C, DPLL1 is freq lock, phase not lock. The register 0x3006 is 0xb, it means REFAA missing? Why 0x3200 shows DPLL1's freq lock when REFAA missing?

Then, I have changed DPD level from 2ns to 5ns, The state register 0x3200 is changed between 0x2c and 0x2f.

The test waveform is as follows:

The orange is OUT1A 30.74MHz.

The blue is OUT1A 1PPS.

The green is REFAA 1PPS.

The test waveform is triggered by OUT1A.

Attached is changed cso file, please help to check it.

AD9545_0308.zip

Look forward to your reply！

Thanks!

HI,

the fact that register 0x3006 does not have bit 4 set to 1 (REFAA valid) and is equal to 0xB is not good at all. For the DPLL1 to work (i.e. to become active), REFAA must be valid continuously. It is strange that the DPLL1 is frequency locked. It shows REFAA is valid for long periods of time . Now I see you set DPLL1 with two identical profiles based on REFAA. Please disable the DPLL1 Profile 1. It does not make sense.

What instrument are you using to generate 1PPS? I recommend starting with a real 1Hz signal generator (at least a rubidium based one), create the AD9545 configuration, get it to work. Then, you replace it with a GPS module. Triggering the scope on the 1Hz output and seeing jitter on the 1PPS input does not help us to conclude anything. The reason is that some GPS modules have a quantization error that make the 1PPS output to have a low frequency jitter. The DPLL tries to lock onto whatever reference is provided and this makes scope captures look  like yours. You need to trigger onto a rubidium based 1Hz clock and observe the 1PPS GPS clock jitter relative to that clock. That will tell you the jitter of the 1PPS. Then, after we solve the AD9545 configuration, you add the 1Hz AD9545 output and compare it against the 1PPS while triggering on the rubidium 1Hz. You'll then see the 1Hz output follows the 1PPS within the 5ns threshold you set .

Several other comments: 

- did you get the auxiliary DPLL to lock? Does register 0x3002 have the bit 1 set to 1?

- put REFAA valid flag to one of the Mx pins and probe it with an oscilloscope. You can see how the AD9545 considers it in real time.

- put the oscilloscope probe on REFAA pin and see if the 1PPS clock has the right 1.8V CMOS levels specified at page 13, rev C AD9545 data sheet:

Petre

Hi Petre,

      Thanks for your comments.

      I use GPS module to generate the 1PPS, I will try to replace it with 1Hz signal generator according to your suggestion.

    For other comments:

- The register 0x3002 is 0x01, bit1 is 0 , The auxiliary DPLL is not lock. How to help the auxiliary DPLL to lock? I have tested M0 pin OCXO, its signal is OK.

-REFAA pin signal's high level is 1.79V, and low level is 0.036V, it meets 1.8V CMOS level SPEC.

Thanks!

HI,

the fact the auxiliary DPLL does not lock is very strange. Please check register 0x3002, bit 2. If it is 1, as I expect, it means the reference clock is not valid, so the OCXO clock is not OK. The M0 voltage levels depend on the VDDIOA or VDDIOB supply level:

If REFAA levels are correct, then the period is not consistent. The REFAA monitor accepts only 100,000 ppb offset, which for 1 Hz clock means 100 us. It may signify the period has variations greater than 100us, which is quite a lot. Did you put the REFAA valid flag at one of the Mx pins to check it with an oscilloscope as I recommended yesterday?

I did not ask, but I hope you calibrate the system clock PLL and the analog PLLs and you follow the initialization procedure outlined in the rev C data sheet at page 164

Petre

Hi Petre,

      The register 0x3002 is 0x05, Bit 2 is 1 as you expect. The VDDIOA and VDDIOB is supplied by 3.3V power, and I have tested OCXO' signal at M0 pin, it seems have not problem. OCXO' clock signal is as follows:

    The register 0x3001 is shifted back and forth between 0x23 and 0x03, the register 0x3200 is shifted back and forth between 0x2f and 0x2c. However the register 0x3006 is 0xb, it's strange.

   I want to put refAA valid flag at  M6 pin as you recommend, but ACE software reports error. It is as follows:

   The AD9545 is configured by EEPROM during power up in our board, how to calibrate the system clock PLL and the analog PLLs?

  My CSO file is as follows, please help to check whether it has any errors.Thanks!

AD9545_0316.zip

Look forward to your reply！

Thanks!

HI,

the register 0x3002 being 0x05 is not good. Bit 2 being 1 means the auxiliary reference clock is not valid.

This is a buffered register, so you need to execute a IO Update first in order to get the right value. See attached a document listing the live and buffered registers.

PDF

Did you do a IO Update before reading this register?

The fact the register 0x3001 shows PLL1 unlocked checks what the register 0x3200 shows that DPLL1 phase locks and then unlocks. This is consistent with the system clock not being stable. This in my view shows you have to concentrate to get the OCXO clock at M0 pin to be considered valid. The 3.3V level seems fine. 

The registers 0x3001 and 0x3200 are live registers. The register 0x3006 is a buffered one. Did you use IO Update before reading 0x3006? The value 0x0B indicates the signal is not present at the pin.

The M6 pin is muxed with SPI pin CSB. Do you then use I2C to communicate with the AD9545? I set M6 as an output with REFAAMON_VALID flag and I also got an event error. We never look at the additional windows in ACE. I am not convinced they matter. Test first with M6 pin set HIGH or LOW and see that it replicates the setting from ACE.

"The AD9545 is configured by EEPROM during power up in our board, how to calibrate the system clock PLL and the analog PLLs?"

You have too many things going on. Leave alone the EEPROM for now and get the configuration going. Then you can concentrate on the EEPROM. There is an application note about the EEPROM management: AN-2072 (https://www.analog.com/en/products/ad9545.html#product-documentation)

At page 10 of this application note, you can see that after the 10 system clock registers starting at address  0x200 are written, an IO Update is executed and then the system clock PLL is calibrated

Then, at the end, the analog PLLs are calibrated:

Petre

HI,

the register 0x3002 being 0x05 is not good. Bit 2 being 1 means the auxiliary reference clock is not valid.

This is a buffered register, so you need to execute a IO Update first in order to get the right value. See attached a document listing the live and buffered registers.

PDF

Did you do a IO Update before reading this register?

The fact the register 0x3001 shows PLL1 unlocked checks what the register 0x3200 shows that DPLL1 phase locks and then unlocks. This is consistent with the system clock not being stable. This in my view shows you have to concentrate to get the OCXO clock at M0 pin to be considered valid. The 3.3V level seems fine. 

The registers 0x3001 and 0x3200 are live registers. The register 0x3006 is a buffered one. Did you use IO Update before reading 0x3006? The value 0x0B indicates the signal is not present at the pin.

The M6 pin is muxed with SPI pin CSB. Do you then use I2C to communicate with the AD9545? I set M6 as an output with REFAAMON_VALID flag and I also got an event error. We never look at the additional windows in ACE. I am not convinced they matter. Test first with M6 pin set HIGH or LOW and see that it replicates the setting from ACE.

"The AD9545 is configured by EEPROM during power up in our board, how to calibrate the system clock PLL and the analog PLLs?"

You have too many things going on. Leave alone the EEPROM for now and get the configuration going. Then you can concentrate on the EEPROM. There is an application note about the EEPROM management: AN-2072 (https://www.analog.com/en/products/ad9545.html#product-documentation)

At page 10 of this application note, you can see that after the 10 system clock registers starting at address  0x200 are written, an IO Update is executed and then the system clock PLL is calibrated

Then, at the end, the analog PLLs are calibrated:

Petre

Hi Petre,

          I did not do a IO update before I read these registers. I have read these register again after IO update. The register 0x3002 is 0x03, it shows the Aux DPLL is locked. The register 0x3006 is 0x10, it shows the REFAA is valid. The GPS's 1PPS(REFAA INPUT) jitter is about 27ns, My DPD threshold  is 5ns, it maybe the cause why DPLL phase can't be locked.

        Thanks!

HI,

these are good news in relation to AuxDPLL and REFAA validity. 

I am curious how you measured the jitter on REFAA=1PPS. 

Regarding the DPD phase lock threshold: see what your application needs in terms of how close the 1Hz output must be to the 1PPS reference. Then set that value to the phase lock threshold.

 Maybe you can find a 1Hz rubidium or cesium based generator just to demonstrate for yourself that the AD9545 configuration works. Then you can focus on the GPS module and its related jitter

Petre