Hi, I'm having AD9516-4 with input ref clock 100MHz differential, the input ref clock is not detected inside AD9516-4(Observed form configuring REFMON to R-divider output and the result is constant LOW), I'm having another AD9516-3 which has the same input ref clk(a TI cdclv1204 lvds buffer output ref clk to each AD9516, AC-coupled with 0.1uF cap) and it works alright for AD9516-3(Observed form configuring REFMON to R-divider output and the result is a positive pulse of 100MHz / R_divide_value period), and AD9516-3 PLL is LOCK(though VCO clk phase noise is not good enough)
While checking hardware I find AD9516-4 self-bias voltage on input ref clk(probe of oscilloscope is on ad9516 side of AC-coupling capacitor) is only ~0.8V, according to datasheet it should be about 1.3V to 1.7V, I also measure AD9516-3 the self-bias voltage is 1.5V/1.6V on p/n side and this is right in accordance with the description of datesheet.During testing AD9516-3 I also find when removing input ref clk, the self-bias voltage the drops from 1.5V to GND, when input ref clk is valid again the self-bias voltage remains about 0V and does not go back to 1.5V, and the PLL/VCO does not lock again, unless I reconfigure AD9516 through FPGA.
I have the following 2 questions,
1. Is my AD9516-4 0.8V self-bias voltage mean this AD9516-4 IC chip is damaged(not correctly functioning)? Or do you have some advices on how to debug this prolem(the input ref clock is not detected inside AD9516-4). Though the SPI interface seems functioning alright.
2. Why the self-bias voltage the drops from 1.5V to GND when removing input ref clk, and why it does not go back to 1.5V when input ref clk is valid again?
Thanks a lot
