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AD9516-3 output clk has very bad phase-noise, but input ref clk quality is fine enough

Hi, I'm having ad9516-3 output 2GHz clk(direct output from VCO), reference clk is 100MHz differential.

The input ref clk, output clk and ad9516 register configuration is showed in figures below. As we can see, phase noise of output clk is awfully bad...But we check our hardware and software and it seems the configuration is not wrong. What's your advice on how to indentify the reason and fix the problem? Thanks

Ref 100MHz clk, differential, picture below shows clk_p, clk_n is acturally the same(~800mV V-pp)

ad9516 out0_p side, awfully bad pahse noise

  • HI,

    first of all, you are not outputting 2GHz at OUT0. You are outputting 2097.1520MHz. 

    Please give me more details about the board you use: is it the evaluation board? Is it your board?

     Did the PLL lock onto the reference?

    I'll see if I can replicate this on an evaluation board, so I can send you a configuration that was verified.


  • Hi it's my own board, AD9516-3 is configured through FPGA, DLD(observing from pin LD) is constant high so I guess PLL is locked onto the reference. Is there any testpoint or method that I can diagnose and figure out why VCO output has such bad phase noise/jitter? 

    Also attached my configuration of AD9516-3 below, as you can see, there are 64 times of ad9516 register writing operations in sequence, the value of each reg is generated from AD9516 evaluation software

    entity AD9516_3_Brom is
        Port ( clk : in STD_LOGIC;
               addr : in STD_LOGIC_VECTOR (5 downto 0);
               dout : out STD_LOGIC_VECTOR (23 downto 0));
    end AD9516_3_Brom;
    architecture Behavioral of AD9516_3_Brom is
    	type mem is array ( 0 to 2**6 - 1) of std_logic_vector(23 downto 0);
    constant my_rom : mem := (                                                                
        0=>x"0000BD",   --000, soft rst
        1=>x"000099",   --000, MSB, SDO act
        2=>x"00107C",   --010, 4.8mA, pll on
        3=>x"00116A",   --011, R divider(LSB 8bits): 0x71
        4=>x"001218",   --012, R divider(MSB 6bits): 256*0x02
        5=>x"001300",   --013, A counter(6 bits): 0x00				--14
        6=>x"001400",   --014, B counter(LSB 8bits): 0x00			--7F
        7=>x"001510",   --015, B counter(MSB 5bits): 256*0x10	--01
        8=>x"001606",   --016, Vcp/2, R/A/B normal, P by 32
        9=>x"0017AC",   --017, status pin
        10=>x"001900",  --019, default0x00
        11=>x"001A00",  --01A, LD status
        12=>x"001B05",  --01B, REFMON status
        13=>x"001C01",  --01C, REFX, REF_SEL pin, REF1 on, REF2 on, single REF
        14=>x"001D00",  --01D, holdover disable(default)
        15=>x"001E00",  --01E, blank reg
        16=>x"001806",  --018, VCO cal standby, VCO cal div: 16
        17=>x"023201",  --232, update reg
        18=>x"01E002",  --1E0, VCO divider: 2
        19=>x"01E102",  --1E1, VCO as input, VCO divider not bypass
        20=>x"00A001",  --0A0, out6 delay bypass(default)
        21=>x"00A100",  --0A1, out6 ramp current(default)
        22=>x"00A200",  --0A2, out6 delay, 0
        23=>x"00A301",  --0A3, out7 delay bypass
        24=>x"00A400",  --0A4, out7 ramp
        25=>x"00A500",  --0A5, out7 delay 0
        26=>x"00A601",  --0A6, out8 delay bypass
        27=>x"00A700",  --0A7, out8 ramp
        28=>x"00A800",  --0A8, out8 delay 0
        29=>x"00A901",  --0A9, out9 delay bypass
        30=>x"00AA00",  --0AA, out9 ramp
        31=>x"00AB00",  --0AB, out9 delay 0
        32=>x"00F008",  --0F0, out0 LVPECL 780mV, power on
        33=>x"00F108",  --0F1, out1 LVPECL 780mV, power on
        34=>x"00F208",  --0F2, out2 LVPECL 780mV, power on
        35=>x"00F308",  --0F3, out3 LVPECL 780mV, power on			--0A
        36=>x"00F40A",  --0F4, out4 LVPECL 400mV, safe power down	--08
        37=>x"00F50A",  --0F5, out5 LVPECL 600mV, power on			--0A
        38=>x"014042",  --140, out6 LVDS, 3.5mA, 100R, power on
        39=>x"014142",  --141, out7 LVDS, 3.5mA, 100R, power on		--43
        40=>x"014243",  --142, out8 LVDS, 3.5mA, 100R, power on
        41=>x"014343",  --143, out9 LVDS, 3.5mA, 100R, power on		--43
        42=>x"019000",  --190, divider0, 2
        43=>x"019180",  --191, divider0 bypass, phase offset 0
        44=>x"019202",  --192, out0/1 connect to divider0, duty-cycle correction enable
        45=>x"019300",  --193, divider1, 2
        46=>x"019480",  --194, divider1 bypass, phase offset 0
        47=>x"019502",  --195, out2/3 connect to divider1, duty-cycle correction enable
        48=>x"019600",  --196, divider2, 2
        49=>x"019780",  --197, divider2 not bypass, phase offset 0
        50=>x"019800",  --198, out4/5 connect to divider2, duty-cycle correction enable
        51=>x"019977",  --199, divider3.1, 4
        52=>x"019A00",  --19A, divider3.1/3.2, phase offset 0
        53=>x"019B11",  --19B, divider3.2, 2
        54=>x"019C00",  --19C, divider 3.1 not bypass, divider 3.2 bypass
        55=>x"019D00",  --19D, divider3 duty-cycle correction enable
        56=>x"019E77",  --19E, divider4.1, 4
        57=>x"019F00",  --19F, divider4.1/4.2, phase offset 0
        58=>x"01A011",  --1A0, divider4.2, 2
        59=>x"01A100",  --1A1, divider 4.1 not bypass, divider 4.2 bypass
        60=>x"01A200",  --1A2, divider4 duty-cycle correction enable
        61=>x"023201",  --232, update reg
        62=>x"001807",  --018, VCO cal initiate, VCO cal divider 16
        63=>x"023201"   --232, update reg
                wait until clk='1' and clk'event;
            end process;
    end Behavioral;

  • VCO status is also constant high(observing from pin LD configured as VCO status) 

  • Hi,

    I played in the lab with the AD9516-3 evaluation board set as you intend. I got a very bad 2.097152 MHz output at OUT0. Then, instead of creating 2.097152MHz output, I created only 2GHz using a PFD frequency equal to 10MHz. The 2Ghz output had 408 fs jitter, in line with results in Table 9 in the data sheet.

    I then increased the REF1 divider to 100 (PFD=1MHz) and the 2GHz output remained cleaned. But when I increased the REF1 divider to 1000 (PFD=100kHz), the 2GHz output began to have noise. When I set the divider to 10k, the 2GHz output had even greater noise.

    My recommendation is to use a greater PFD frequency. If the 2.097152 GHz output is a must, then try to provide a different REF1 frequency, one that can raise the PFD frequency above 1MHz.


  • Thanks for the detailed explanation, I'll try to figure out what to do. Also can I ask that do you have some recommandation of which IC chips(Either ADI or TI) that you known for sure that would work fine generatiing eg. like 2.097152GHz from 100MHz ref?

  • Hi,

    you can consider the AD9520-2. I took an evaluation board. I supplied 100MHz, 4dBm from a Rohde & Schwartz SMA 100A generator at REF1. I configured it as attached (take out the txt extension) to generate 2.097152GHz LVPECL at OUT0. I obtained this, which looks consistent with a typical performance plot from the data sheet. 

    "AD9520 Setup File"
    "Other Settings..."
    "REF 1:",100
    "REF 2:",30.72
    "Auto Update:",1
    "Load All Regs:",1
    "CheckSum Values"
    "8-Bit Device Checksum (uses R0x000 to R0x232): ","0x6EA"
    "8-Bit Data Pattern Checksum (all regs): ","0xB3C"
    "16-Bit Device Checksum (uses R0x000 to R0x232): ","0x37479"
    "16-Bit Data Pattern Checksum (all regs): ","0x5DE63"