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HMC7044 pll1 can not lock


  I want to use evaluation board for a test.  10Mhz refclock added CLKIN1,OSCIN is 122.88Mhz(CVHD-950 on board).now it can detect refcolck,but cann't lock pll1.
 my ADIsimCLK configuration as follows:

and read register state is(sometime 0x0085 is 0x06):

Can you give me some advice?Thanks in advance.

  • Hi,

    Can you share your register settings so that I can check? This is probably related with the PLL1 divider settings or OSCIN prescaler output. If you are not setting OSCIN prescaler, default setting (4) can cause the issue. 

    The OSCIN prescaler output should be equal or close to reference prescaler output. If you are using 122.88 MHz on OSCIN, setting OSCIN prescaler value to 10 will possbily solve the issue. 



  • 		dut_write(0x0, 0x0);
    		dut_write(0x1, 0x0);
    		dut_write(0x2, 0x0);
    		dut_write(0x3, 0x37);
    		dut_write(0x4, 0x7F);
    		dut_write(0x5, 0x4F);
    		dut_write(0x6, 0x0);
    		dut_write(0x7, 0x0);
    		dut_write(0x9, 0x1);
    		dut_write(0xA, 0x7);
    		dut_write(0xB, 0x7);
    		dut_write(0xC, 0x7);
    		dut_write(0xD, 0x7);
    		dut_write(0xE, 0x7);
    		dut_write(0x14, 0xE4);
    		dut_write(0x15, 0x3);
    		dut_write(0x16, 0xC);
    		dut_write(0x17, 0x0);
    		dut_write(0x18, 0x4);
    		dut_write(0x19, 0x0);
    		dut_write(0x1A, 0x1);
    		dut_write(0x1B, 0x18);
    		dut_write(0x1C, 0x1);
    		dut_write(0x1D, 0x1);
    		dut_write(0x1E, 0x4);
    		dut_write(0x1F, 0x1);
    		dut_write(0x20, 0x0c);
    		dut_write(0x21, 0x7d);
    		dut_write(0x22, 0x0);
    		dut_write(0x26, 0x00);
    		dut_write(0x27, 0x6);
    		dut_write(0x28, 0xf);
    		dut_write(0x29, 0x5);
    		dut_write(0x2A, 0x0);
    		dut_write(0x31, 0x1);
    		dut_write(0x32, 0x0);
    		dut_write(0x33, 0x40);
    		dut_write(0x34, 0x0);
    		dut_write(0x35, 0x71);
    		dut_write(0x36, 0x2);
    		dut_write(0x37, 0xF);
    		dut_write(0x38, 0x18);
    		dut_write(0x39, 0x0);
    		dut_write(0x3A, 0x0);
    		dut_write(0x3B, 0x0);
    		dut_write(0x46, 0x0);
    		dut_write(0x47, 0x0);
    		dut_write(0x48, 0x9);
    		dut_write(0x49, 0x11);
    		dut_write(0x50, 0x37);
    		dut_write(0x51, 0x33);
    		dut_write(0x52, 0x0);
    		dut_write(0x53, 0x0);
    		dut_write(0x54, 0x3);
    		dut_write(0x5A, 0x0);
    		dut_write(0x5B, 0x6);
    		dut_write(0x5C, 0x0);
    		dut_write(0x5D, 0x1);
    		dut_write(0x64, 0x0);
    		dut_write(0x65, 0x0);
    		dut_write(0x70, 0x0);
    		dut_write(0x71, 0x10);
    		dut_write(0x78, 0x0);
    		dut_write(0x79, 0x0);
    		dut_write(0x7A, 0x0);
    		dut_write(0x7B, 0x0);
    		dut_write(0x7C, 0x0);
    		dut_write(0x7D, 0x0);
    		dut_write(0x7E, 0x0);
    		dut_write(0x82, 0x0);
    		dut_write(0x83, 0x0);
    		dut_write(0x84, 0x0);
    		dut_write(0x85, 0x0);
    		dut_write(0x86, 0x0);
    		dut_write(0x8C, 0x0);
    		dut_write(0x8D, 0x0);
    		dut_write(0x8E, 0x0);
    		dut_write(0x8F, 0x0);
    		dut_write(0x91, 0x0);
    		dut_write(0x96, 0x0);
    		dut_write(0x97, 0x0);
    		dut_write(0x98, 0x0);
    		dut_write(0x99, 0x0);
    		dut_write(0x9A, 0x0);
    		dut_write(0x9B, 0xAA);
    		dut_write(0x9C, 0xAA);
    		dut_write(0x9D, 0xAA);
    		dut_write(0x9E, 0xAA);
    		dut_write(0x9F, 0x4D);//LYT
    		dut_write(0xA0, 0xDF);    //LYT
    		dut_write(0xA1, 0x97);
    		dut_write(0xA2, 0x3);
    		dut_write(0xA3, 0x0);
    		dut_write(0xA4, 0x0);
    		dut_write(0xA5, 0x06);//LYT
    		dut_write(0xA6, 0x1C);
    		dut_write(0xA7, 0x0);
    		dut_write(0xA8, 0x06);//LYT
    		dut_write(0xA9, 0x0);
    		dut_write(0xAB, 0x0);
    		dut_write(0xAC, 0x20);
    		dut_write(0xAD, 0x0);
    		dut_write(0xAE, 0x8);
    		dut_write(0xAF, 0x50);
    		dut_write(0xB0, 0x4);//LYT
    		dut_write(0xB1, 0xD);
    		dut_write(0xB2, 0x0);
    		dut_write(0xB3, 0x0);
    		dut_write(0xB5, 0x0);
    		dut_write(0xB6, 0x0);
    		dut_write(0xB7, 0x0);
    		dut_write(0xB8, 0x0);
    		dut_write(0xC8, 0xF3);
    		dut_write(0xC9, 0xF0);
    		dut_write(0xCA, 0x0);
    		dut_write(0xCB, 0x0);
    		dut_write(0xCC, 0x0);
    		dut_write(0xCD, 0x0);
    		dut_write(0xCE, 0x0);
    		dut_write(0xCF, 0x0);
    		dut_write(0xD0, 0x1);
    		dut_write(0xD2, 0xFC);
    		dut_write(0xD3, 0x0);
    		dut_write(0xD4, 0x1);
    		dut_write(0xD5, 0x0);
    		dut_write(0xD6, 0x0);
    		dut_write(0xD7, 0x0);
    		dut_write(0xD8, 0x0);
    		dut_write(0xD9, 0x0);
    		dut_write(0xDA, 0x30);
    		dut_write(0xDC, 0xF3);
    		dut_write(0xDD, 0x18);
    		dut_write(0xDE, 0x0);
    		dut_write(0xDF, 0x0);
    		dut_write(0xE0, 0x0);
    		dut_write(0xE1, 0x0);
    		dut_write(0xE2, 0x0);
    		dut_write(0xE3, 0x0);
    		dut_write(0xE4, 0x1);
    		dut_write(0xE6, 0xFC);
    		dut_write(0xE7, 0x0);
    		dut_write(0xE8, 0x1);
    		dut_write(0xE9, 0x0);
    		dut_write(0xEA, 0x0);
    		dut_write(0xEB, 0x0);
    		dut_write(0xEC, 0x0);
    		dut_write(0xED, 0x0);
    		dut_write(0xEE, 0x30);
    		dut_write(0xF0, 0xF3);
    		dut_write(0xF1, 0x30);
    		dut_write(0xF2, 0x0);
    		dut_write(0xF3, 0x0);
    		dut_write(0xF4, 0x0);
    		dut_write(0xF5, 0x0);
    		dut_write(0xF6, 0x0);
    		dut_write(0xF7, 0x0);
    		dut_write(0xF8, 0x1);
    		dut_write(0xFA, 0xFC);
    		dut_write(0xFB, 0x0);
    		dut_write(0xFC, 0x1);
    		dut_write(0xFD, 0x0);
    		dut_write(0xFE, 0x0);
    		dut_write(0xFF, 0x0);
    		dut_write(0x100, 0x0);
    		dut_write(0x101, 0x0);
    		dut_write(0x102, 0x30);
    		dut_write(0x104, 0xF3);
    		dut_write(0x105, 0xC);
    		dut_write(0x106, 0x0);
    		dut_write(0x107, 0x0);
    		dut_write(0x108, 0x0);
    		dut_write(0x109, 0x0);
    		dut_write(0x10A, 0x0);
    		dut_write(0x10B, 0x0);
    		dut_write(0x10C, 0x1);
    		dut_write(0x10E, 0xFC);
    		dut_write(0x10F, 0x0);
    		dut_write(0x110, 0x1);
    		dut_write(0x111, 0x0);
    		dut_write(0x112, 0x0);
    		dut_write(0x113, 0x0);
    		dut_write(0x114, 0x0);
    		dut_write(0x115, 0x0);
    		dut_write(0x116, 0x30);
    		dut_write(0x118, 0xF3);
    		dut_write(0x119, 0x2);
    		dut_write(0x11A, 0x0);
    		dut_write(0x11B, 0x0);
    		dut_write(0x11C, 0x0);
    		dut_write(0x11D, 0x0);
    		dut_write(0x11E, 0x0);
    		dut_write(0x11F, 0x0);
    		dut_write(0x120, 0x1);
    		dut_write(0x122, 0xFD);
    		dut_write(0x123, 0x0);
    		dut_write(0x124, 0x1);
    		dut_write(0x125, 0x0);
    		dut_write(0x126, 0x0);
    		dut_write(0x127, 0x0);
    		dut_write(0x128, 0x0);
    		dut_write(0x129, 0x0);
    		dut_write(0x12A, 0x30);
    		dut_write(0x12C, 0xF3);
    		dut_write(0x12D, 0x2);
    		dut_write(0x12E, 0x0);
    		dut_write(0x12F, 0x0);
    		dut_write(0x130, 0x0);
    		dut_write(0x131, 0x0);
    		dut_write(0x132, 0x0);
    		dut_write(0x133, 0x0);
    		dut_write(0x134, 0x1);
    		dut_write(0x136, 0xFD);
    		dut_write(0x137, 0x0);
    		dut_write(0x138, 0x1);
    		dut_write(0x139, 0x0);
    		dut_write(0x13A, 0x0);
    		dut_write(0x13B, 0x0);
    		dut_write(0x13C, 0x0);
    		dut_write(0x13D, 0x0);
    		dut_write(0x13E, 0x30);
    		dut_write(0x140, 0xF3);
    		dut_write(0x141, 0x10);
    		dut_write(0x142, 0x0);
    		dut_write(0x143, 0x0);
    		dut_write(0x144, 0x0);
    		dut_write(0x145, 0x0);
    		dut_write(0x146, 0x0);
    		dut_write(0x147, 0x0);
    		dut_write(0x148, 0x1);
    		dut_write(0x14A, 0xFD);
    		dut_write(0x14B, 0x0);
    		dut_write(0x14C, 0x1);
    		dut_write(0x14D, 0x0);
    		dut_write(0x14E, 0x0);
    		dut_write(0x14F, 0x0);
    		dut_write(0x150, 0x0);
    		dut_write(0x151, 0x0);
    		dut_write(0x152, 0x30);
    I copied them out to here

  • Hi,

    Register settings seems correct but you are using very low PFD frequency for PLL1 and this is causing a drastic change in the loop filter response. I missed it in first look but your phase margin 6.74 degree. This is why your loop is unstable and not locking. You can change loop filter component values and get a better phase margin value around 50-60 degree. This will provide lock on PLL1.

    My other suggestion is to switch your VCXO from 122.88 MHz to 100 MHz. 

    Your reference clock is 10 MHz, you can just use 10 MHz PFD in PLL1 to lock VCXO. Also, you want to generate 2400 MHz fundamental VCO frequency. To do that, you are again using very low PFD frequency on PLL2 which will degrade your output phase noise performance. If you use 100 MHz VCXO, you can enable doubler and use 200 MHz PFD frequency, this will provide ~15 dB improvement in your in-band noise, huge difference. 

    Crystek has 100 MHz variant in CVHD-950 family. This is pin compatible with 122.88 MHz version you are using right now. So, you won't need any hardware change. 

    Let me know if this does not help.


  • Hi,
      Thank you so much! The problem has been solved. I have another problem. I want to output 10MHz, 50MHz, 100MHz, 200MHz and 500MHz. At the same time, I need ultra-low phase noise frequency. If cvhd-950 100MHz (or others) is used,  what parameters of 7044 or indicators of CLKIN (oscin) shall I need to pay attention to,  in order to achieve this purpose? I use adisimclk simulation and find that it is difficult to meet the following phase noise requirements @ 10MHz:

    -85dBc/hz @1Hz

    -120dBc/hz @10Hz

    -140dBc/hz @100Hz

    -150dBc/hz @1kHz

    -155dBc/hz @10kHz

    I would appreciate it if you could give me some advice!

  • Hi,

    Since you are aiming very low offsets, the noise will be mostly dominated by VCXO and PLL 1/f noise. You can use ADISIMCLK to determine the specs of VCXO which can satisfy the above phase noise values.