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AD9528 CLK input

I want to drive CLK inputs of the ADRV9026 by using AD9528.

SYSREF JESD204 and baseband clocks will be drived by outputs of the AD9528.

Therefore, I will supply a cyrstal CLK input to AD9528.

Can I drive REFA and VCXO_IN inputs of the AD9528 with a clipped sine CLOCK?

Is using a CMOS signal a must in these inputs?



grammar mistake corrected
[edited by: bugra01 at 11:09 AM (GMT -5) on 24 Feb 2022]
  • HI,

    It's a good choice to use the AD9528 to clock the ADRV9026. Many people do it.

    "Therefore, I will supply a cyrstal CLK input to AD9528"

    The AD9528 does not accept crystal resonators as inputs. If you want to apply a clock from an oscillator to the AD9528, just apply it to the VCXO_IN pins and use only PLL2. Use the cleanest XO that you can find because the PLL2 bandwidth is around 500kHz and this means a lot of noise of the XO will be reflected at the outputs

    "Can I drive REFA and VCXO_IN inputs of the AD9528 with a clipped sine CLOCK?"

    Yes, but please ensure the clock has a slew rate greater than 500V/us, per data sheet specifications table.

    And please note that we like the VCXO_IN clock to be dc coupled, so the ac coupled capacitors in an ac coupled approach do not affect the phase noise of that clock.

    "Is using a CMOS signal a must in these inputs?"

    Not for REFA. See comments above for the VCXO_IN.

    I recommend using ADIsimCLK to simulate the AD9528 together with your VCXO or XO and see the phase noise of the outputs for various VCXO_IN clocks.

    https://www.analog.com/en/design-center/adisimclk.html

    Petre