Post Go back to editing

AD9528 VCXO Input

AD9528 has a VCXO input described as PLL1 oscillator input.

I want to use AD9528 for two reasons:

1-) SYSREF JESD204B clock generation (internally)

2-) Multiplexing baseband clock input that is applied to REFA pin

(REFA input will be drived with 40MHz clipped sine wave and I want to get 245MHz at the output)

Should I use an external VCXO and apply to VCXO IN?

What should be  properties of VCXO?

What frequency range can I apply to this input?



additional explanations for REFA input are added
[edited by: bugra02 at 8:19 AM (GMT -5) on 17 Feb 2022]
  • 00Hi,

    you could enter with 40MHz into VCXO_IN pins and use PLL2 to obtain 245MHz at the output:

    The PLL2 loop bandwidth should be around 500kHz, so the 245MHz output phase noise will be determined mainly by the cleanliness state of the 40 MHz.

    Then if you use a for example, 160MHz VCXO, you could use PLL1. Usually the PLL1 has a loop bandwidth set below 100Hz, in order to clean the 40 MHz reference and "confer" it the VCXO phase noise. So in this case, the 245MHz output will mainly have the characteristics of the VCXO and of the PLL2 VCO.

    Petre