• State Not Answered
  • Replies 1 reply
  • Subscribers 145 subscribers
  • Views 124 views
  • Users 0 members are here
Options
Related 

        

            Post
             Go back to editing
        

    

    


    

    









		











	
	
			
	
			
		
	
	
		

		
AD9528 baseband clock and JESD240B



		

			

									
						bugra01
					
							

			
				
									
											
							 		
		        	            							
			
			    	
			                    
                
				                on Feb 7, 2022 
				
			
			
		


				
		

		    		    
		    
		    	
			
I want to divide a TCXO source by using REFA and OUT1, OUT2, OUT3, OUT4 of AD9528.


But in the datasheet of the AD9528, there is no information about its frequency stability.


Since frequency stability is important for me, I used TCXO which provides low PPM values.


How can I assure that AD9528 does not increase PPM values beyond the levels I anticipate?




Also, do I need an external clock while creating JESD204B clock (SYSREF)?

								


				
				
		

			
						
									
									
						
						
			
			
			
			
		


					

			





	

		
	











	

	

					



			


				
	









	
    
	

  • 
	
    



	
		
	
	



    
	
    
		
    
							
					
    
		
    
			
													0
							
			
				
									
							        
            
                                                                                                        
      
                            
    • 
                                 Analog Employees 
                                
                            
      • 
                        
     
                                                           			
			                            
                        
                on Feb 9, 2022 6:57 PM
            
            
					
    
	
    

		
		
    
					
    Hi,
    

    you say the TCXO clock is applied to REFA. So you intend to use PLL1 and PLL2. PLL1 should be configured with a loop bandwidth below 100 Hz and PLL2 should be configured with a loop bandwidth around 500kHz.
    

    Frequency stability can be viewed as a very low frequency spur attached to the nominal frequency, a spur with a much lower  frequency than 1Hz. Because of this, the AD9528 PLL2 output replicates the very low frequency spurs present into REFA. So my recommendation is not to worry about the stability of the AD9528 outputs. Just provide at REFA a clock with the stability you desire for the AD9528 outputs.
    

    "do I need an external clock while creating JESD204B clock (SYSREF)?"
    

    No, there is a SYSREF generator that can generate SYSREF derived from the VCXO clock or from the PLL2 feedback clock. See page 34 in rev E AD9528 data sheet
    

    Petre
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

    •