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HMC7044 SYNC pin


I am using a HMC7044 in a custom board.

The HMC is connected to a 10MHz oscillator through OSCIN input. It is configured to use the high VCO to generate a frequency of 3GHz.

The sysref timer divider is set to 1200, so it is configured to 2.5Mhz.

In the clock output network, I am using two outputs, the first one divides the VCO clock 24 times to generate 125MHz, the second one divides the VCO clock 300 times to generate 10 MHz.

In other device of the board, the 125Mhz clock provided by the HMC7044 is divided by two and its phase changes, and I need to rephase the 10MHz output of the HMC7044 with the phase of a trigger generated with the external 62.5 MHz clock. I am connecting the trigger to the SYNC input of the HMC7044, and enabling the SYNC only in the channel that generates the 10MHz clock.

I can see the 10MHz clock and the trigger in an oscilloscope, when the trigger signal rises, the 10MHz clock provided by the HMC7044 changes its phase to a random position.

Is there a way to implement this mechanism in a deterministic way?

This is my setup:

This is what I obtain, a random phase between 10Mhz clk and the rising edge of the sync signal that is different every power cycle of the HMC7044:

  • power cycle 1 (22 nanoseconds):

  • power cycle 2 (26 nanoseconds): 

I need a deterministic phase between the 10Mhz clk and the rising edge of the sync signal that remains the same every power cycle of the HMC7044.

Thanks in advance.

Detailed description
[edited by: Jorge_mac at 12:09 PM (GMT -5) on 24 Jan 2022]
  • Hi,

    Can you share your register settings and your write sequence? I wonder if you are making initial synchronization between 125 MHz and 10 MHz clocks. Are you enabling the SYNC bit of 125 MHz channel at the beginning?

    Also, the deterministic latency is defined with OSCIN to output. Important timing is between the first rising edge of OSCIN after the SYNC pulse and the first rising edge of 10 MHz clock. Can you also probe be OSCIN input? 


  • Hi Kudret, thanks for your response.

    Find the register write sequence in the attached file. The registers are written through the HMC7044 Linux driver.

    [   10.176448] writing reg 0x00000000 with value 0x00000001
    [   10.186488] writing reg 0x00000000 with value 0x00000000
    [   10.201824] writing reg 0x000000c8 with value 0x00000000
    [   10.207149] writing reg 0x000000d2 with value 0x00000000
    [   10.212485] writing reg 0x000000dc with value 0x00000000
    [   10.217810] writing reg 0x000000e6 with value 0x00000000
    [   10.223143] writing reg 0x000000f0 with value 0x00000000
    [   10.228471] writing reg 0x000000fa with value 0x00000000
    [   10.233855] writing reg 0x00000104 with value 0x00000000
    [   10.239220] writing reg 0x0000010e with value 0x00000000
    [   10.244585] writing reg 0x00000118 with value 0x00000000
    [   10.249949] writing reg 0x00000122 with value 0x00000000
    [   10.255279] writing reg 0x0000012c with value 0x00000000
    [   10.260606] writing reg 0x00000136 with value 0x00000000
    [   10.265937] writing reg 0x00000140 with value 0x00000000
    [   10.271265] writing reg 0x0000014a with value 0x00000000
    [   10.276634] writing reg 0x0000009f with value 0x0000004d
    [   10.282000] writing reg 0x000000a0 with value 0x000000df
    [   10.287365] writing reg 0x000000a5 with value 0x00000006
    [   10.292737] writing reg 0x000000a8 with value 0x00000006
    [   10.298103] writing reg 0x000000b0 with value 0x00000004
    [   10.303475] writing reg 0x00000005 with value 0x00000042
    [   10.317449] writing reg 0x00000003 with value 0x0000002f
    [   10.317513] writing reg 0x00000033 with value 0x00000001
    [   10.322842] writing reg 0x00000034 with value 0x00000000
    [   10.328170] writing reg 0x00000035 with value 0x00000096
    [   10.333502] writing reg 0x00000036 with value 0x00000000
    [   10.338830] writing reg 0x00000032 with value 0x00000000
    [   10.344162] writing reg 0x0000001a with value 0x00000008
    [   10.349490] writing reg 0x00000028 with value 0x0000000f
    [   10.354822] writing reg 0x0000001c with value 0x00000001
    [   10.360150] writing reg 0x0000001d with value 0x00000019
    [   10.365482] writing reg 0x0000001e with value 0x00000001
    [   10.370809] writing reg 0x0000001f with value 0x00000001
    [   10.376141] writing reg 0x00000020 with value 0x00000004
    [   10.381508] writing reg 0x00000021 with value 0x00000001
    [   10.386873] writing reg 0x00000022 with value 0x00000000
    [   10.392246] writing reg 0x00000026 with value 0x00000004
    [   10.397612] writing reg 0x00000027 with value 0x00000000
    [   10.402975] writing reg 0x00000014 with value 0x000000e4
    [   10.408341] writing reg 0x00000029 with value 0x00000005
    [   10.413705] writing reg 0x0000005c with value 0x000000b0
    [   10.419035] writing reg 0x0000005d with value 0x00000004
    [   10.424362] writing reg 0x0000005a with value 0x00000000
    [   10.429695] writing reg 0x0000000a with value 0x00000000
    [   10.435022] writing reg 0x0000000b with value 0x00000000
    [   10.440355] writing reg 0x0000000c with value 0x00000000
    [   10.445682] writing reg 0x0000000d with value 0x00000000
    [   10.451015] writing reg 0x0000000e with value 0x00000003
    [   10.456342] writing reg 0x00000046 with value 0x00000000
    [   10.461675] writing reg 0x00000047 with value 0x00000000
    [   10.467003] writing reg 0x00000048 with value 0x00000000
    [   10.472334] writing reg 0x00000049 with value 0x00000000
    [   10.477663] writing reg 0x00000050 with value 0x0000001f
    [   10.483030] writing reg 0x00000051 with value 0x0000002b
    [   10.488397] writing reg 0x00000052 with value 0x00000000
    [   10.493761] writing reg 0x00000053 with value 0x00000000
    [   10.509126] writing reg 0x000000c9 with value 0x0000001e
    [   10.514488] writing reg 0x000000ca with value 0x00000000
    [   10.519857] writing reg 0x000000d0 with value 0x00000010
    [   10.525182] writing reg 0x000000cb with value 0x00000000
    [   10.530514] writing reg 0x000000cc with value 0x00000000
    [   10.535842] writing reg 0x000000cf with value 0x00000000
    [   10.541174] writing reg 0x000000c8 with value 0x00000081
    [   10.546502] writing reg 0x000000d3 with value 0x00000030
    [   10.551841] writing reg 0x000000d4 with value 0x00000000
    [   10.557170] writing reg 0x000000da with value 0x00000010
    [   10.562503] writing reg 0x000000d5 with value 0x00000000
    [   10.567831] writing reg 0x000000d6 with value 0x00000000
    [   10.573163] writing reg 0x000000d9 with value 0x00000000
    [   10.578490] writing reg 0x000000d2 with value 0x00000081
    [   10.583823] writing reg 0x000000fb with value 0x0000002c
    [   10.589189] writing reg 0x000000fc with value 0x00000001
    [   10.594554] writing reg 0x00000102 with value 0x0000001b
    [   10.599918] writing reg 0x000000fd with value 0x00000000
    [   10.605284] writing reg 0x000000fe with value 0x00000000
    [   10.610647] writing reg 0x00000101 with value 0x00000000
    [   10.616014] writing reg 0x000000fa with value 0x000000c1
    [   10.621340] writing reg 0x000000dd with value 0x00000001
    [   10.626672] writing reg 0x000000de with value 0x00000000
    [   10.632000] writing reg 0x000000e4 with value 0x00000008
    [   10.637332] writing reg 0x000000df with value 0x00000000
    [   10.642660] writing reg 0x000000e0 with value 0x00000000
    [   10.647992] writing reg 0x000000e3 with value 0x00000000
    [   10.653320] writing reg 0x000000dc with value 0x00000081
    [   10.658652] writing reg 0x000000e7 with value 0x0000002c
    [   10.663980] writing reg 0x000000e8 with value 0x00000001
    [   10.669313] writing reg 0x000000ee with value 0x00000008
    [   10.674640] writing reg 0x000000e9 with value 0x00000000
    [   10.679972] writing reg 0x000000ea with value 0x00000000
    [   10.685300] writing reg 0x000000ed with value 0x00000000
    [   10.690667] writing reg 0x000000e6 with value 0x00000081
    [   10.696035] writing reg 0x0000010f with value 0x00000030
    [   10.701399] writing reg 0x00000110 with value 0x00000000
    [   10.706762] writing reg 0x00000116 with value 0x00000001
    [   10.712128] writing reg 0x00000111 with value 0x00000000
    [   10.717492] writing reg 0x00000112 with value 0x00000000
    [   10.722822] writing reg 0x00000115 with value 0x00000000
    [   10.728149] writing reg 0x0000010e with value 0x000000c1
    [   10.733482] writing reg 0x00000137 with value 0x00000030
    [   10.738809] writing reg 0x00000138 with value 0x00000000
    [   10.744141] writing reg 0x0000013e with value 0x00000010
    [   10.749469] writing reg 0x00000139 with value 0x00000000
    [   10.754802] writing reg 0x0000013a with value 0x00000000
    [   10.760129] writing reg 0x0000013d with value 0x00000000
    [   10.765465] writing reg 0x00000136 with value 0x00000081
    [   10.770789] writing reg 0x00000141 with value 0x0000002c
    [   10.776129] writing reg 0x00000142 with value 0x00000001
    [   10.781459] writing reg 0x00000148 with value 0x00000010
    [   10.786790] writing reg 0x00000143 with value 0x00000000
    [   10.792118] writing reg 0x00000144 with value 0x00000000
    [   10.797489] writing reg 0x00000147 with value 0x00000000
    [   10.802851] writing reg 0x00000140 with value 0x000000c1
    [   10.808221] writing reg 0x0000014b with value 0x00000018
    [   10.813589] writing reg 0x0000014c with value 0x00000000
    [   10.818953] writing reg 0x00000152 with value 0x00000010
    [   10.824325] writing reg 0x0000014d with value 0x00000000
    [   10.829657] writing reg 0x0000014e with value 0x00000000
    [   10.834984] writing reg 0x00000151 with value 0x00000000
    [   10.840317] writing reg 0x0000014a with value 0x00000081
    [   10.855646] writing reg 0x00000001 with value 0x00000002

    Enabling the SYNC in the 125MHz channel does not solve my problem, because the phases of the
    125MHz and 62.5 MHz external clock (which is generating the SYNC) are different.

    In my board, the HMC7044 OSCIN pin is connected to a 10MHz oscillator. Is the SYNC granularity then 100 ns?

  • Hi,

    As I can see, you are disabling the "SYNC Enable" bit of SCLK13 at the beginning. Also, you re not sending a Reseed Request to part to align its outputs. You need to:

    - Enable "SYNC Enable" bit of all channels that you use. 

    - Send Restart Request by writing Reg0x01[1]=1 and Reg0x01[1]=0

    - Send Reseed Request by writing Reg0x01[7]=1 and Reg0x01[7]=0

    - Disable "SYNC Enable" bit of SCLK13 (125 MHz channel). 

    - Send SYNC pulse from your external device. 


  • Hi Kudret,

    In the HMC7044 datasheet, the Reg0x01[0] bit means "sleep request".

    Do I have use that bit to send a restart request? or I must use Reg0x01[1] "Restart dividers/FSM"

  • Thanks for the warning. Edited my reply.