I am using a HMC7044 in a custom board.
The HMC is connected to a 10MHz oscillator through OSCIN input. It is configured to use the high VCO to generate a frequency of 3GHz.
The sysref timer divider is set to 1200, so it is configured to 2.5Mhz.
In the clock output network, I am using two outputs, the first one divides the VCO clock 24 times to generate 125MHz, the second one divides the VCO clock 300 times to generate 10 MHz.
In other device of the board, the 125Mhz clock provided by the HMC7044 is divided by two and its phase changes, and I need to rephase the 10MHz output of the HMC7044 with the phase of a trigger generated with the external 62.5 MHz clock. I am connecting the trigger to the SYNC input of the HMC7044, and enabling the SYNC only in the channel that generates the 10MHz clock.
I can see the 10MHz clock and the trigger in an oscilloscope, when the trigger signal rises, the 10MHz clock provided by the HMC7044 changes its phase to a random position.
Is there a way to implement this mechanism in a deterministic way?
This is my setup:
This is what I obtain, a random phase between 10Mhz clk and the rising edge of the sync signal that is different every power cycle of the HMC7044:
- power cycle 1 (22 nanoseconds):
- power cycle 2 (26 nanoseconds):
I need a deterministic phase between the 10Mhz clk and the rising edge of the sync signal that remains the same every power cycle of the HMC7044.
Thanks in advance.
[edited by: Jorge_mac at 12:09 PM (GMT -5) on 24 Jan 2022]