1. I am using AD9528 to generate clocks for AD9375.
2. Reference clock used is 10 MHz. Output Frequency of interest is 122.88 MHz(Device Clock) & 0.96 MHz (Sysref)
3. I followed this approach from the following Link.
https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/167648/adrv9008-1-sampling-freq-selection and the attached snipshot is for your reference.
4. Kindly let us know the external Loop filter components of PLL for this approach!
[edited by: Manikandan_M_M at 2:51 PM (GMT -5) on 18 Jan 2022]