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ADF4372 Fs/2 and 3Fs/2 Clock Spurious

Hello ADI Team,

I am using ADF4372 PLL for generating Output Clock with frequency 12.288 GHz in Doubler path (RF16).

PLL Settings:

Reference input frequency is 409.6 MHz.

PFD frequency = 307.2 MHz

VCO Frequecny = 6.144GHz

PLL Output Observation:

I observed the Doubler path Output Clock 12.288GHz @ power -12.25dBm with following Additional frequency products (VCO and 3xVCO)

1. Spurious Signal1 (VCO) = 6.144GHz @-40.14dBm (-52.39dBc with Fundamental clock power)

2. Spurious Signal1 (3xVCO) = 18.432 GHz @-40.23dBm  (-52.48dBc with Fundamental clock power)


1. I have seen the following information in datasheet to use tracking filter for suppressing VCO & 3xVCO frequency products.

I set the Register values as mentioned above in Configuration file.

Address Data
0X0023, 0x02
0X0070, 0X43

But still the problem not solved.

2. I turned off RF8x path to avoid VCO coupling. But still problem not solved

Is there any other regiter setting is available to reduce the power level of frequency products (VCO and 3xVCO)?


W	0x0000	0x81	50
W	0x0000	0x00	0
W	0x0001	0x80	0
W	0x0073	0x43	0
W	0x0072	0x02	0
W	0x0070	0xE3	0
W	0x0052	0xF4	0
W	0x0047	0xC0	0
W	0x0041	0x28	0
W	0x0040	0x50	0
W	0x003F	0x80	0
W	0x003E	0x0C	0
W	0x003D	0x00	0
W	0x003A	0x55	0
W	0x0039	0x07	0
W	0x0038	0x00	0
W	0x0037	0x00	0
W	0x0036	0x30	0
W	0x0035	0xFF	0
W	0x0034	0x85	0
W	0x0033	0x02	0
W	0x0032	0x04	0
W	0x0031	0x02	0
W	0x0030	0x2B	0
W	0x002F	0x0A	0
W	0x002E	0x0A	0
W	0x002D	0x09	0
W	0x002C	0x24	0
W	0x002B	0x01	0
W	0x002A	0x00	0
W	0x0028	0x83	0
W	0x0027	0xFD	0
W	0x0026	0x05	0
W	0x0025	0x8A	0
W	0x0024	0x80	0
W	0x0023	0x02	0
W	0x0022	0x50	0
W	0x0020	0x1C	0
W	0x001F	0x02	0
W	0x001E	0x58	0
W	0x0012	0x40	0
W	0x0011	0x00	0
W	0x0010	0x3C	0

Please provide your support.

Thanks in advance,


ADF4372 Spurious image uploaded
[edited by: Harishh at 8:11 AM (GMT -5) on 8 Jan 2022]