I'm currently looking at the HDL for adrv9009zu11eg/adrv2crr_fmc and I wanted to know what the adc clock is to integrate my HW accelerators to.
I'm transitioning from fmcomms2 project which used the ad9361 and for that project I used the clk_div_out for all my DSP.
I wanted to know what's the equivalent clk_div_out for adrv9009zu11eg/adrv2crr_fmc.
My assumption is that its core_clk_a_1 and core_clk_b1 for RX1 and RX2 respectfully.
Is my assumption correct?