In my system I will usually have an external 10 MHz reference signal to which I must lock my internal PLL.
When this external 10 MHz signal disappears, I must maintain the same output frequency.
To achieve this functionality I intend to use the AD9557 with the Holdover functionality.
With this solution (tested on the evaluation board), I keep the output frequency when the external reference disappears and if it reappears, I lock to it again.
My problem arises when the new external reference is not exactly the same, but there is a small difference lower than 1 Hz. (my ouput frequency is near 30 GHz)
In that case, when I connect the new reference, I notice a jump in the output frequency of the system.
I need this frequency displacement to be less than 0.2 ppm/sg. Is there any way to limit the speed of the DPLL adjustment?
Is there any other model you can recommend for this functionality?
Best regards and thanks in advance