AD9361 Side band spur


My board shows side band spur on ref CLK freq away from my TX freq.

I am using 30.72MHz external CLK as a reference and the spur position is 30.72Mhz away from my TX.

I tried several registers related this and I found when 0X009 D4 is cleared even though I use ext CLK the spur improves more than 10dB.

Multiple boards shows same so I was using with the bit cleared.

Today I found a board act reverse way.

The unit shows the Spur with the bit cleared and when I set the bit to 1 the spur gone away.

Now I think, the bit (0X009 D4) control may not be a final solution. 

Do you have any better solution? 

The related pictures are in below.

It is measured on ANT port (LTE band 1 UL TX).

The TX is on low edge area of the band and the left side spur is rejected by frontend filter and not shown on this picture. 

When I use high edge freq for TX, spur positioned on left side shows up.

The spur level is about 60dB below from my main TX.