Hello,
My customer use AD9549 and ask some question about AD9549 output clk frequency in their below test result.
They set AD9549 PLL output with S/R Devider x4, and then test below conditions.
1) If source is 25MHz, output of AD9549 is exact 100MHz. (25x4 = 100)
2) But if source is 49.952Mhz, output of AD9549 is 199.840MHz, not 199.808MHz. (49.953 x 4 = 199.808)
Q1) Is above result correct? ( Source input is a 10 bit digitized signal.)
Q2) Would you let me know whty this difference is occurred?
Is this a PLL characteristic? conversion error? error from PPM?
or need to review schematic & configuration? device fault?
Please advise me.
Regards,
Se-woong