driving ad9523-1 with FPGA

HI,

I suppose you created a configuration stp file from which you extracted the register values you used to configure the AD9523-1 on your board.

Please send me this stp file, so I can take a look.

Now, I suppose the I2C communication works, in the sense that you have verified that you can write and read back the registers. Did you do this? For example, there are many registers that have a non zero default value. Were you able to read them correctly?

 Then, the device initialization figure 46 from page 41 in rev A data sheet shows that at least one of the reference clocks must be applied to the chip after power up before the chip initialization can begin. Did you do this?

I assume you read the register 0x22C correctly, but the fact the bit 6 (PLL2 feedback clock) is 0, that is the PLL2 feedback clock is missing is strange. If you calibrated PLL2 VCO, the VCO should work and the PLL2 feedback clock should be OK. 

So I would start with verifying the I2C communication works. Then I would put the oscilloscope probe on REFA, REFB and VCO OSC_IN pins and see is the clocks meet the specification in the data sheet. 

If you want, you may send me the schematic to take a look

Petre

Hi Petre

thanks for the support.

Yes i can read the default value of registers correctly. also i have a delay power up before initialization start. at the end of initialization process, the VCO calibration takes place. 

actually i figured out the problem, but now I'm facing another one. the reason that i couldn't detect my inputs was that when i try to write  to the POWER_UP REGISTER,   to enable PLL1, PLL2 and DISTRIBUTION(defaults are powered down), the PLL2 can't be powered on and forces all the POWER_UP REGISTER to it's default value! so AD9523-1 was almost disable. now I can power up PLL1 and DISTRIBUTION  and I'm having 0X"6C" on  0X"22C" REGISTER. I don't Know why PLL2 is disabled. I thought that it can be because of VCO bandwidth so i use ADIsimclock to calculate the dividers and RZERO for PLL1 and PLL2. i have updated them into may VHDL program but the problem still exists. one more thing, the OSC_CTRL pin(VCXO CONTROL) always is about 1V and doesn't change to lock the PLL2. my VCXO frequency range is 10 to 40 MHZ and now is always 10MHZ. also REFA is 25MHZ and REFB is 50MHZ.

thank you for your advices

Hi,

I asked you to send me the stp file and you did not do it. 

It's basically very difficult for me to help you without looking at stp file.

Please also send me the VCXO data sheet to see what VCXO you use.

The PLL2 may be not configured correctly because it is strange that the VCXO is OK, but the PLL2 reference clock is not.

The data sheet states the OSC_CTRL pin is min VDD3_PLL-0.15 min with a load of more than 20 kohm. With VDD3_PLL being 3.3V, this makes 3.15V min, not 1V. Please send me the schematic as well to verify it. 

OSC_CTRL pin locks PLL1, not PLL2. 

Petre

hi, 

sorry i have attached VCXO datasheet, AD9523-1 schematic and a file with registers setting.

thanks

PDFjitter_cleaner.rar

HI,

I introduced the register values into the AD9523-1 eval software (you could have zipped or rar-ed the stp file to attach it directly). I found several issues:

- not clear what is the VCXO nominal output frequency. The data sheet states the VCXO has a 3.3V CMOS output. I do not have a license for Altium to see your schematic. Please make a pdf file of the schematic and send it to me. I expect the VCXO output to be connected to the OSC_IN pin based on the register settings.

- the charge pump current of PLL1 is set in tri-state mode, so the PLL1 cannot work to close the loop. I set it to Normal operation. The default value of 6uA current is OK.

- based on register settings, I expect REFA and REFB to be single ended and provided at the REFA and REFB pins (not the REFA\ and REFB\ ones).

- the PLL1 feedback divider is set to 1, so I expect the VCXO to be 25 MHz. I set the REFB divider to 2.

- the PLL2 charge pump current was set to 0, which is not correct. I ste this current to the max value, 892.5uA

- the feedback divider of PLL2 was set to 52, which made for a PLL2 VCO frequency lower than 2900MHz. I increased the divider to 61 (because the PLL2 had the doubler enabled), so now the PLL2 VCO is 3100MHz, the max value.

- if you tell me what outputs you want to obtain, I can set the PLL2 VCO frequency accordingly and I can also set the outputs correctly

I attach the new stp file I created. I did not test it on a board because I do not have one with VCXO of 25 MHz, but it should work.

AD9523_1_setup.zip

See how this one goes

Petre

Hi dear petre

thank you for your support. 

I followed your Advices  about charge pump, loop filters and VCO frequency and understand my mistakes. actually i think  the VCXO  that i'm using is not proper for this design . I was reading your comment on another question, about hold over mode. so now  I am feeding the OSC_IN with a 125MHZ clock signal, and disabled the PLL1. I have updated the registers according to your comments and PLL2 is locked. I have X"E2" on "022C" register. the VCO frequency is 3GHz and VCO dividers is set on 3.so i have a 1 GHz output from VCO . now i have 2 questions: 

1- i need  a 1MHz signal so i set the channel dividers on 1000 but i could not see any output(distribution is on). is there anything i have missed?

2-  how good is jitter clearance and output quality in hold over mode?

many thanks

AD9523-1 schematics PDF

Hi,

I'm glad you got at least PLL2 locked and now you can move forward.

You may not see the 1MHz output because one or more of these reasons:

- you need to set a driver mode in registers 0x190 to 0x1B9.

- the schematic does not show any termination on the outputs, so I assume you want to use the outputs as CMOS. But if you want LVPECL, LVDS or HSTL you need to put a 100 ohm load resistor. See figures at page 20 in revA data sheet.

- you need to generate a SYNC command using one of the following methods:

"how good is jitter clearance and output quality in hold over mode?"

In holdover mode, the PLL generates an output without being locked, so it does not do any cleaning. The outputs have the performance determined fully by the PLL2 VCO.

I looked at the schematic you sent: all REFA, REFB, OSC_IN are single ended, dc coupled. Make sure the clocks at the pins meet this specification:

You connected the OSC_CTRL pin directly to the VCXO. Normally a filter would be used. See the evaluation board schematic.

I trust the loop filter you use was simulated in the ADIsimCLK. It is different from the one on the evaluation board.

Petre

hi 

thank you petre for your advices. it worked. now i have 1MHZ output. 

i will try to lock PPL1 later. but it's enough for me now.

BR

hi 

thank you petre for your advices. it worked. now i have 1MHZ output. 

i will try to lock PPL1 later. but it's enough for me now.

BR