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Timing Error with AD9083 project (util_adxcvr) - K26 Xilinx

Hi,

We are working with a default Analog Devices project to receive information from its ADC (ADC9083) through the JESD204B (Subclass 1) protocol. The default project is created for the zcu102 board but we have modified the files to export it for the SOM k26, which belongs to the Zynq UltraScale + family (part number: xck26-sfvc784-2lv-c) and a Zynq UltraScale+ 4EG component (part number: xczu4eg-sfvc784-2-e).

In the case of 4EG we have had no problems when implementing and exporting the bitstream. But for the xck26 we are having timing errors:

To solve the rx_out_clk_s timing error, we have used the Ultrascale + FPGAs Transceiver Wizard: (wiki.analog.com/.../xgt_wizard) setting the reception Line Rate to 12Gb / s, QPLL1, and the rest of the default values . When you click OK, a component is generated and a Generate Outputs window appears.

When looking for the files referred to in the above link, (gtwizard_ultrascale_v1_7_gthe4_common.v, gth_jesd204_gthe4_common_wrapper.v, gtwizard_ultrascale_v1_7_gthe4_channel.v and  gth_jesd204_gthe4_channel_wrapper.v) don't appear in the designated path because the path (<project>.srcs/sources_1/ip/gth_jesd204/synth) don't exist. They do appear in the path: <project>.gen/sources_1/ip/gth_jesd204/synth.

We have replaced the values ​​of the parameters of the ad9083_evb_bd.tcl file with the values ​​of the previous files, using only the wrapper files because it contains the necessary attributes of the configuration set in the Wizard.

When re-implementing it, there are timing errors greater than with the initial configuration. What can it be due to?

Is it only necessary to modify the util_adxcvr parameters that are instantiated in ad9083_evb_bd.tcl, or would it be necessary to include all the parameters of the util_adxcvr module?

Thank you so much.



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[edited by: IvanRios at 8:00 AM (GMT -5) on 17 Nov 2021]