Post Go back to editing

ADF4372- Clock Generation in Fractional Mode

Hello ADI Team,

I am using ADF4372 PLL for generating Output Clock with frequency 12451.84 MHz in Doubler path (RF16).

Reference input frequency is 409.6 MHz

PFD Frequency is 102.4MHz

Hence N divider value is 60.8.

What will be value for INT, FRAC1, MOD2 and FRAC2.

As per the calculation in datasheet, I calculated, I am getting floating number for FRAC2.

Is it possible to generate 12451.84MHz with 102.4MHz PFD frequency?

Thanks in advance,


Parents Reply Children