AD9545 setup questions

Hello

              Some questions as below. 

  1. Below figure is captured from AD9545 datasheet. Which Mx pin function should be set for 1 PPS input?
  2. If OCXO is connected to REFBB, we can enable AuxDPLL compensation for DPLLx, AuxNCOx, and TDCs? All component can stabilize by OCXO? How to select bandwidth value?
  3. 8273.2 needs 0.05-0.1Hz loss-pass filter, does this setting at DPLL profile x loop bandwidth?
  4. Base on cso file you provide to us, DPLL1 will synchronize to DPLL0. Do we need to change loop bandwidth in profile1.0?
  5. If ptp packet lost then we need OCXO to stable output clock, does this function done by item 2

https://drive.google.com/file/d/1ayIqMTtCkmysnoB_R5_AqZMVw6JGRWgv/view?usp=sharing 

 

Attachment is revised cso file. SYS IN can use crystal (52MHz) or OCXO(30.72MHz) through BOM select.

BR

Patrick

  • Hello

            Have any comments for above? Thank you for support. 

    BR

    Patrick

  • Hi Patrick, I will discuss Monday/Tuesday and coordinate with information that Jim supplied as well.  I apologize for the delay.  Expect a response by our end-of-business on Tuesday.

  • HI,

    The figure you want to discuss is from the AD9545 rev B data sheet, page 159. 

    Now, responding to your specific questions:

    1. Below figure is captured from AD9545 datasheet. Which Mx pin function should be set for 1 PPS input?

    Any M0, M1 or M2 can be used. M3 may be used at power up to start the EEPROM download if it is high. M4 selects the serial port. I suppose the SPI is the serial port that will be used, and we recommend using the 3 -wire flavor, which frees  the pin M5. M6 is used as CSB for SPI.

     

    1. If OCXO is connected to REFBB, we can enable AuxDPLL compensation for DPLLx, AuxNCOx, and TDCs? All component can stabilize by OCXO? How to select bandwidth value?

    Yes, use a 52 MHz crystal resonator to create the system clock and use a 10 MHz or 20 MHz OCXO for the system clock compensation. Then set the AuxDPLL to lock onto REBB=OCXO with 50 Hz bandwidth and to compensate the DPLLs, AuxNCOs and TDCs.

     

    1. 8273.2 needs 0.05-0.1Hz loss-pass filter, does this setting at DPLL profile x loop bandwidth?

    This standard refers to low pass filters of 0.1Hz bandwidth when measuring clock outputs. The DPLL loop bandwidth should be set to at least 20 times less than the DPD frequency of the DPLL.

     

    1. Base on cso file you provide to us, DPLL1 will synchronize to DPLL0. Do we need to change loop bandwidth in profile1.0?

    I also presented a new approach, using the AuxNCO0 as the reference clock for both DPLLs. The bandwidth should still be 50 Hz.

     

    1. If ptp packet lost then we need OCXO to stable output clock, does this function done by item 2

    Yes, the system clock compensation will make sure the DPLL outputs remain as stable as the OCXO.

     Petre

  • Hello Petre

              Have one question. Do we have our own servo algorithm software? Thank you. 

    BR

    Patrick