What are the specifications and estimation method for the output frequency accuracy of the clock generator?

Hi all,

What are the specifications and estimation method for the output frequency accuracy of the clock generator?

Our customers are comparing the following two clock generators as candidate devices for new development projects.
AD9576, AD9577

We could not find a specification for output frequency accuracy on any of the devices.
How should we consider the specifications and estimation method of the output frequency accuracy of AD9576 and AD9577?
Please give us some advice.

An example of a competing device below is the output frequency accuracy specification.
TI: CDCM6208
www.ti.com/.../cdcm6208.pdf 253DCDCM6208V1HRGZR

Output frequency error; Fractional output divider: –1 (min) 1 (max) ppm

Best Regards,
sss

Parents
  • Hi,

    the competitor part you mention has an integer PLL and fractional dividers in the distribution output block.

    The AD9576 and AD9577 have one integer PLL and one fractional PLL. The dividers in the distribution output block are all integer.

    From the output accuracy perspective, because the AD9576 and AD9577 have integer dividers in the distribution output block, these dividers do not matter. They divide the VCO output exactly.

    The integer PLL also does not exhibit any frequency error because the VCO output is an integer multiple of the PFD frequency.

    The fractional PLL tuning accuracy depends on the fractional modulus. The AD9576 has a 24 bit modulus, which means an error of 1/2^24=0.06ppm at the VCO output.

    The AD9577 fractional PLL has a 12 bit modulus, which means 1/2^12=244 ppm error at the VCO output. 

    The competitor part you mention has a 20 bit modulus, which means 1/2^20=1ppm error, explaining the data sheet specification.

    If the fractional PLL is set with an integer feedback divider, the VCO output has 0 error.

    Petre

Reply
  • Hi,

    the competitor part you mention has an integer PLL and fractional dividers in the distribution output block.

    The AD9576 and AD9577 have one integer PLL and one fractional PLL. The dividers in the distribution output block are all integer.

    From the output accuracy perspective, because the AD9576 and AD9577 have integer dividers in the distribution output block, these dividers do not matter. They divide the VCO output exactly.

    The integer PLL also does not exhibit any frequency error because the VCO output is an integer multiple of the PFD frequency.

    The fractional PLL tuning accuracy depends on the fractional modulus. The AD9576 has a 24 bit modulus, which means an error of 1/2^24=0.06ppm at the VCO output.

    The AD9577 fractional PLL has a 12 bit modulus, which means 1/2^12=244 ppm error at the VCO output. 

    The competitor part you mention has a 20 bit modulus, which means 1/2^20=1ppm error, explaining the data sheet specification.

    If the fractional PLL is set with an integer feedback divider, the VCO output has 0 error.

    Petre

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