AD9542 REFBB fault

Hi,

the AD9545 register 0x3008 having a value of 0x0A shows bit 1 REFBB Fast being set to 1. This means the REFBB frequency of 30.72MHz is deemed by the AD9545 being higher than allowed. The reference monitor looks at the period of REFBB together with the offset tolerance (in your case, this is at default, 100,000 ppb=100ppm). It calculates a frequency and for some reason, it believes the REFBB frequency is higher than the one calculated using the nominal period minus 100 ppm. 

The data sheet declares a typical common mode voltage of 0.64V, so if you measured 600mV, it signifies is OK. An amplitude of 800mBp-p is also OK because it is greater than 350 mVp-p min specification.

How do you create the system clock? The chip calculates the REFBB frequency based on the belief the system clock configuration matches the reality. Maybe you have a problem with the system clock source.

Petre

Hello Petre

    If both channels set to open loop, how to synchronize both channels? Customer plan to use DPLL0 as master, update FTW to DPLL0 by ptp4l. Then how DPLL1 synchronize to DPLL0? Do we need to update FTW of DPLL1 also?

    Or it can be done by setting DPLL compensation? Thank you. 

BR
Patrick

Hi,

I am sorry, please tell me exactly what you need because your questions sequence confuses me. Please tell me what you need to do with the 30.72 MHz reference and what outputs you need to obtain.

Then I'll respond to the question regarding the synchronization of the outputs.

The DPLL compensation you mention refers to compensating the system clock and making it as stable as a reference clock. If, for example, DPLL0 uses a reference clock that is generated by an OCXO, so it is very stable, then every change in the DPLL0 tuning word is a reflection of the wonder of the system clock. I can measure that change and calculate a compensation factor that I can then use to correct the tuning word of DPLL1 and eliminate the influence of the system clock wonder. I can also compensate the auxiliary NCOs and the TDCs. It is not related to synchronizing the DPLL1 outputs to the DPLL0 outputs

Petre

Hello Petre

   Sorry to cause your confuse. They are different questions to customer. Customer would like to know how to synchronize both channels if both channels set to open loop? 

   if use DPLL0 as master, how DPLL1 synchronize to DPLL0 while update FTW to DPLL0 by ptp4l?  Do you have suggestion for it? Thank you. 

BR

Patrick  

Hi,

I recommend proceeding in this way:

- set DPLL0 in freerun.  

- set DPLL1 to lock onto an auxiliary NCO in internal zero delay mode

- take a Channel 0 output and bring it to one of Mx pins. Divide it inside the AD9545 down to below 200kHz. Assign it to Auxiliary TDC 0.

- take a Channel 1 output of the same frequency and bring it to another Mx pin. Divide it inside the AD9545 down to the same frequency as the other clock from Channel 0. Assign it to Auxiliary TDC 1.

- read the time stamps of Aux TDC0 and Aux TDC1

-calculate the frequency of the clock at Aux TDC0 and another of the clock at Aux TDC1.

- calculate a frequency difference and a phase offset between the clocks represented by the time stamps at Aux TDC0 and Aux TDC1.

- use the frequency difference to adjust the Aux NCO frequency. This will bring Channel 1 output to have the same frequency as the Channel 0 output

- use the phase offset to adjust the auxiliary NCO phase offset. This will bring Channel 1 output to be aligned in phase to the Channel 0 output

Petre

Hello Petre

Attachment is .cso file plan to be used in customer project, REF, SYS IN, and OUT frequency has been configured.

Could you please help to apply setting you provide below into the .cso file?

The device theyare using is AD9542, I am doubt that it cannot support IEEE1588 specification. Could you comment it?

https://drive.google.com/file/d/1HDwC8FfMQLJB571yqyIdW6MtIhULXHED/view?usp=sharing 

 Customer reply as below: 

- set DPLL0 in freerun. 

>>OK

- set DPLL1 to lock onto an auxiliary NCO in internal zero delay mode 

>>How to set it?

- take a Channel 0 output and bring it to one of Mx pins. Divide it inside the AD9545 down to below 200kHz. Assign it to Auxiliary TDC 0. 

>>Need external connection from OUT0 to one of Mx?  How to divide it inside AD9542?

- take a Channel 1 output of the same frequency and bring it to another Mx pin. Divide it inside the AD9545 down to the same frequency as the other clock from Channel 0. Assign it to Auxiliary TDC 1.

>>Output of channel 1 and channel 0 are different frequency, how to meet this requirement?

- read the time stamps of Aux TDC0 and Aux TDC1 

>>Does AD9542 has this function?

Hi,

the AD9542 does not contain the auxiliary NCOs, so you cannot use it. Now you started to talk about 1588. Why is it difficult to give me all the details from the beginning?

I recommend to use the AD9545 for creating the program and then select the AD954x chip that will be used ultimately.

I took your AD9542 setting and moved it to the AD9545.

- I assumed you provide a 30.72 MHz clock at XOA/XOB pins. Is this the OCXO you were talking to being provided at REFBB? We recommend another approach: use a crystal resonator of 52 MHz to create the system clock, thus obtaining outputs with the best phase noise possible. Then apply a low frequency OCXO (30.72MHz is fine, but it can be 20 MHz or 10 MHz if is it cheaper)  at one of the references or Mx pins and use it to stabilize the influence of the system clock.

- I enabled the Aux NCO0 with a frequency of 30.72kHz, a frequency that is a divisor of the 245.76 MHz DPLL1 outputs.

- I set the DPLL0 to lock onto REFA in order to create a profile. Otherwise you cannot set it in freerun. Then I checked the Force freerun box in the DPLL0 Settings. Then I clocked Apply button.

- I set DPLL1 to lock onto an auxiliary NCO in internal zero delay mode

- take a Channel 0 output and bring it to one of Mx pins. Divide it inside the AD9545 down to below 200kHz. Assign it to Auxiliary TDC 0.

- take a Channel 1 output of the same frequency and bring it to another Mx pin. Divide it inside the AD9545 down to the same frequency as the other clock from Channel 0. Assign it to Auxiliary TDC 1.

Because the Aux TDC dividers are up to 256, you need outputs with frequencies equal to the AD9545 access frequency the controller can keep multiplied by a factor lower than 256. Let's start with a TDC frequency of 100 Hz. I then choose OUT0B=25 kHz and OUT1B=24 kHz (I replaced OUT1B=245.76MHz).

You then take an AD9508 buffer and you apply OUT0B and create a 1.8V CMOS output that you apply at M0. Then take another AD9508 buffer and apply OUT1B and create a 1.8V CMOS output that you apply at M1.

Look at the cso file I attach at sections M-pin settings and Auxiliary TDC settings for the details.

- read the time stamps of Aux TDC0 and Aux TDC1. Read AD9545 rev B data sheet, page 129 for details.

-calculate the frequency of the clock at Aux TDC0 and another of the clock at Aux TDC1. Subtract consecutive time stamps and you calculate the period.

- calculate a frequency difference and a phase offset between the clocks represented by the time stamps at Aux TDC0 and Aux TDC1.

- use the frequency difference to adjust the Aux NCO frequency (page 131 in the AD9545 rev B data sheet). This will bring Channel 1 output to have the same frequency as the Channel 0 output

- use the phase offset to adjust the auxiliary NCO phase offset (page 132 in the AD9545 rev B data sheet). This will bring Channel 1 output to be aligned in phase to the Channel 0 output

 AD9545_proposed_setup.zip

Petre

Hi,

the AD9542 does not contain the auxiliary NCOs, so you cannot use it. Now you started to talk about 1588. Why is it difficult to give me all the details from the beginning?

I recommend to use the AD9545 for creating the program and then select the AD954x chip that will be used ultimately.

I took your AD9542 setting and moved it to the AD9545.

- I assumed you provide a 30.72 MHz clock at XOA/XOB pins. Is this the OCXO you were talking to being provided at REFBB? We recommend another approach: use a crystal resonator of 52 MHz to create the system clock, thus obtaining outputs with the best phase noise possible. Then apply a low frequency OCXO (30.72MHz is fine, but it can be 20 MHz or 10 MHz if is it cheaper)  at one of the references or Mx pins and use it to stabilize the influence of the system clock.

- I enabled the Aux NCO0 with a frequency of 30.72kHz, a frequency that is a divisor of the 245.76 MHz DPLL1 outputs.

- I set the DPLL0 to lock onto REFA in order to create a profile. Otherwise you cannot set it in freerun. Then I checked the Force freerun box in the DPLL0 Settings. Then I clocked Apply button.

- I set DPLL1 to lock onto an auxiliary NCO in internal zero delay mode

- take a Channel 0 output and bring it to one of Mx pins. Divide it inside the AD9545 down to below 200kHz. Assign it to Auxiliary TDC 0.

- take a Channel 1 output of the same frequency and bring it to another Mx pin. Divide it inside the AD9545 down to the same frequency as the other clock from Channel 0. Assign it to Auxiliary TDC 1.

Because the Aux TDC dividers are up to 256, you need outputs with frequencies equal to the AD9545 access frequency the controller can keep multiplied by a factor lower than 256. Let's start with a TDC frequency of 100 Hz. I then choose OUT0B=25 kHz and OUT1B=24 kHz (I replaced OUT1B=245.76MHz).

You then take an AD9508 buffer and you apply OUT0B and create a 1.8V CMOS output that you apply at M0. Then take another AD9508 buffer and apply OUT1B and create a 1.8V CMOS output that you apply at M1.

Look at the cso file I attach at sections M-pin settings and Auxiliary TDC settings for the details.

- read the time stamps of Aux TDC0 and Aux TDC1. Read AD9545 rev B data sheet, page 129 for details.

-calculate the frequency of the clock at Aux TDC0 and another of the clock at Aux TDC1. Subtract consecutive time stamps and you calculate the period.

- calculate a frequency difference and a phase offset between the clocks represented by the time stamps at Aux TDC0 and Aux TDC1.

- use the frequency difference to adjust the Aux NCO frequency (page 131 in the AD9545 rev B data sheet). This will bring Channel 1 output to have the same frequency as the Channel 0 output

- use the phase offset to adjust the auxiliary NCO phase offset (page 132 in the AD9545 rev B data sheet). This will bring Channel 1 output to be aligned in phase to the Channel 0 output

 AD9545_proposed_setup.zip

Petre

Hello Petre

    Thanks for your support. We will discuss it with customer then get complete information from customer. Thank you. 

BR

Patrick

Hello

       It is the same case and customer change to AD9545 that still have some questions as below thread. Could you help provide suggestion for below? Thank you. 

https://ez.analog.com/clock_and_timing/f/q-a/551770/ad9545-setup-questions 

BR

Patrick

Hi,

discussing here this inquiry, made us find a simpler approach to synchronizing the DPLL channels in free run. when the application requires frequency updates from a servo.

Simply set the AuxNCO0 to 10 kHz (which is the maximum common denominator between the Channel 0 output of 156.25MHz and Channel 1 outputs of 245.76MHz) and set the DPLLs to lock in internal zero delay onto it.

Attached the proposed configuration. 

There are multiple advantages to this approach including the ability to control the loop bandwidth of both DPLLs separately since both DPLL’s are now operating in closed loop mode and referenced to the AuxNCO.  Additionally, if there is an interruption in PTP packet updates, the AuxNCO simply stays at the last updated frequency.  The DPLLs stay locked to the AuxNCO.  Furthermore the AuxNCO can be frequency compensated by another signal such as a SyncE input or a local OCXO to maintain high stability in the absence of PTP packet updates.

PetreAD9545_proposed_setup2.zip