AD9542 REFBB fault

Hello

               Customer use 3.3V OCXO to AD9542 REFBB input via ac coupling as below schematics. but customer read 0x3008 register and value 0xa shows REFBB  fault. But per OCXO waveform, the amplitude = 800mv, offset = 600mV and frequency looks meet specification. Has any comments for REFBB  fault? Thank you. 

BR

Patrick

  • Hi,

    the AD9545 register 0x3008 having a value of 0x0A shows bit 1 REFBB Fast being set to 1. This means the REFBB frequency of 30.72MHz is deemed by the AD9545 being higher than allowed. The reference monitor looks at the period of REFBB together with the offset tolerance (in your case, this is at default, 100,000 ppb=100ppm). It calculates a frequency and for some reason, it believes the REFBB frequency is higher than the one calculated using the nominal period minus 100 ppm. 

    The data sheet declares a typical common mode voltage of 0.64V, so if you measured 600mV, it signifies is OK. An amplitude of 800mBp-p is also OK because it is greater than 350 mVp-p min specification.

    How do you create the system clock? The chip calculates the REFBB frequency based on the belief the system clock configuration matches the reality. Maybe you have a problem with the system clock source.

    Petre

  • Hello Petre

        If both channels set to open loop, how to synchronize both channels? Customer plan to use DPLL0 as master, update FTW to DPLL0 by ptp4l. Then how DPLL1 synchronize to DPLL0? Do we need to update FTW of DPLL1 also?

        Or it can be done by setting DPLL compensation? Thank you. 

    BR
    Patrick

  • Hi,

    I am sorry, please tell me exactly what you need because your questions sequence confuses me. Please tell me what you need to do with the 30.72 MHz reference and what outputs you need to obtain.

    Then I'll respond to the question regarding the synchronization of the outputs.

    The DPLL compensation you mention refers to compensating the system clock and making it as stable as a reference clock. If, for example, DPLL0 uses a reference clock that is generated by an OCXO, so it is very stable, then every change in the DPLL0 tuning word is a reflection of the wonder of the system clock. I can measure that change and calculate a compensation factor that I can then use to correct the tuning word of DPLL1 and eliminate the influence of the system clock wonder. I can also compensate the auxiliary NCOs and the TDCs. It is not related to synchronizing the DPLL1 outputs to the DPLL0 outputs

    Petre

  • Hello Petre

       Sorry to cause your confuse. They are different questions to customer. Customer would like to know how to synchronize both channels if both channels set to open loop? 

       if use DPLL0 as master, how DPLL1 synchronize to DPLL0 while update FTW to DPLL0 by ptp4l?  Do you have suggestion for it? Thank you. 

    BR

    Patrick  

        

                    

  • Hi,

    I recommend proceeding in this way:

    - set DPLL0 in freerun.  

    - set DPLL1 to lock onto an auxiliary NCO in internal zero delay mode

    - take a Channel 0 output and bring it to one of Mx pins. Divide it inside the AD9545 down to below 200kHz. Assign it to Auxiliary TDC 0.

    - take a Channel 1 output of the same frequency and bring it to another Mx pin. Divide it inside the AD9545 down to the same frequency as the other clock from Channel 0. Assign it to Auxiliary TDC 1.

    - read the time stamps of Aux TDC0 and Aux TDC1

    -calculate the frequency of the clock at Aux TDC0 and another of the clock at Aux TDC1.

    - calculate a frequency difference and a phase offset between the clocks represented by the time stamps at Aux TDC0 and Aux TDC1.

    - use the frequency difference to adjust the Aux NCO frequency. This will bring Channel 1 output to have the same frequency as the Channel 0 output

    - use the phase offset to adjust the auxiliary NCO phase offset. This will bring Channel 1 output to be aligned in phase to the Channel 0 output

    Petre