ADRV9009-ZU11EG SOM External Sync Requirements

As SYNCINBx and SYNCOUTBX signals are asynchronous and it goes high or low depending on certain condition. So there is no specific timing requirement and relation to DEV_CLK_IN. 

Refer to below posts:

https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/164320/adrv9009-rf-som-multichip-sync 

Hi,

I'm not sure my question was interpreted correctly, maybe I worded it in a confusing way. I am not asking specifically about ADRV9009s syncing. That should work once the HMC7044's are setup correctly. My questions pertain to getting the HMC7044-CRR phase-sync'd via the SYNC input pin with some specific system constraints. Let me clarify below:

I have an external 50MHz continuous source used as a phase reference input to the HMC7044-CRR. I do not have an associated REF_CLK input to the HMC7044-CRR, so using the HMC7044-CRR in fanout mode is not possible. However, I need to phase-sync the HMC7044-CRR to the 50MHz source somehow. The HMC7044-SOM will be used in fanout mode from the HMC7044-CRR supplied signals.

If I use this 50MHz source as an input to the digital SYNC input signal on the HMC7044-CRR with a 100MHz VCXO:

1. Is the setup/hold time of the SYNC pin met with a 50MHz input and 100MHz VCXO? I couldn't find specifics on this setup/hold time of the input SYNC pin in the HMC7044 datasheet.
2. If the above is yes, then each time the HMC7044-CRR finishes a synchronization event a new one will be triggered since the SYNC input is continuous. This will cause the HMC7044-CRR outputs to toggle on/off, and the will cascade down to the outputs of the HMC7044-SOM since the HMC7044-SOM is in fanout mode. I.e. all the FPGA clocks (core_clk_a/b), ADRV9009 clocks (REF_CLK_ADRV_A/B, SYSREF_ADRV_A/B), and some GTH clocks will be toggled on/off. Once my software verifies the HMC7044-CRR is sync'd, then I would disable all the HMC7044-CRR outputs to be susceptible to SYNC events and thus stop the output toggling. Would the FPGA/ADRV9009's be recoverable after such a sequence of events (i.e. not not be locked-out or stop working till a reboot)? Would reset commands be enough to get the both the FPGA ADRV9009's working again?

Best,

-Samual

Moving to the appropriate forum for comments on HMC7044.

I think I am a bit daft...

Previous revisions of my custom carrier board only included the 122.88MHz VCXO, so PLL1 couldn't be used to phase-lock the VCXO to the integer reference. But rereading that section of the datasheet, it looks like I could feed the reference to the CLKIN0/RFSYNC and make some devicetree changes so that the reference goes through PLL1 to be cleaned up/lock the VCXO to, then the 100MHz VCXO can be used by PLL2 to generate a desired VCO frequency (say 2400MHz). Then with the HMC7044-SOM I can use in fanout mode as desired.

If someone can confirm the above is true, I'll close this thread out.

Thanks much,

-Samual

Hi Samuel,

I’m a bit puzzled why you need the SYNC pin et all.

If you provide a 50MHz reference to the HMC7044-CRR then you’re automatically phase synced.

SYNC is only relevant if you need to synchronized multiple of your HMC7044-CRR->HMC7044-SOM setups.

So to summarize if you have a 100MHz VCXO on the  HMC7044-CRR you can cleanup this reference by PLL1 and PLL2 of the HMC7044-CRR tune it’s VCO to 2400MHz,

And then provide a divide down to the downstream HMC7044-SOM in fanout mode. You need to use CLKIN1/FIN for that purpose. You also provide a sync pulse via CLKIN0/RFSYNC

On the HMC7044-SOM you enable this mode by setting following dt attributes:

                adi,clkin1-vco-in-enable;

                adi,clkin0-rf-sync-enable;

                adi,clkin0-buffer-mode = <HMC7044_CLKIN_LVPECL_100OHM_TERM>; /* My need HW modification - remove AC couble Caps ??? */

                adi,clkin1-buffer-mode = <HMC7044_CLKIN_AC_COUPLING>;

This devicetree here basically does it:

https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-using-clockdist.dts

hmc7044_car uses PLL1, PLL2 and provides a 983.04MHz clock to the downstream HMC7044 in fanout mode.

Best Regards,

Michael

Michael,

Absolutely I do not need the SYNC pin. I was able to modify the devicetree yesterday and get an external reference synced to the HMC7044-CRR successfully.

Previously I only had access to carriers with the 122.88MHz VCXO, so I couldn't easily use an integer reference source without degraded phase noise and didn't really read through the PLL1 section of the datasheet.

I do have a followup question:

When enabling fanout mode in the devicetree for an HMC7044, do the "adi,clkin0-rf-sync-enable" and adi,clkin1-vco-in-enable" properties also disable PLL1/Pll2 as well? Or do I need to separately write the appropriate registers to disable?

Thanks,

-Samual

Samual said:

When enabling fanout mode in the devicetree for an HMC7044, do the "adi,clkin0-rf-sync-enable" and adi,clkin1-vco-in-enable" properties also disable PLL1/Pll2 as well? Or do I need to separately write the appropriate registers to disable?

Please see here: 

https://github.com/analogdevicesinc/linux/blob/88b7d86ff997549cdf24c91edfef24e39e1f34fd/drivers/iio/frequency/hmc7044.c#L1044-L1075

In case adi,clkin1-vco-in-enable; is set both PLLs and the VCO doesn't get enabled.

-Michael

Awesome, thanks as always Michael!

-Samual