I am trying to figure out ways to have synchronous clock signals outputted from two different HMC7044 microcircuits, where skew should be no more than 35 ps.
My system includes two HMC7044, and the signals are synchronized using the SYNC input.
When setting frequency for the first time, clock signals are phase aligned using the built-in delay lines (tuning operation).
Then, I set the frequency again, while having the microcircuits reconfigured and re-writing all the coefficients to the same ones.
Possible results:
1. The measured phase difference is equal to the one, that was obtained during tuning.
2. The measured phase difference is greater than the one, obtained during tuning, by ~ 40 ps.
Reading register 0x008C revealed that obtaining results 1 and 2 depends on different banks of capacitors that were selected by the VCO auto-calibration.
Does anyone know if the algorithm used can be specified and how the capacitor bank gets selected?
Is there other ways to compensate for the phase difference delay, besides taking into account the additional delay, occurring due to selection of a particular capacitor bank?
