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A low jitter(≤100fs) clock generator or PLL ,i need

In my project,

1)ADC is AD9208

2)sample clock=3GHz

3) external refclk is 10MHz

4)use a PLL/CLOCK to generate the sample clock

5)Fin=2.1GHz,SNR=54.19dBFS

6)to implement SNR performance,i use Virtual Eval Tool - BETA ,the external min jitter is 100fs.

so,help me choose a low jitter pll/clock to implement SNR performance

and,if i choose ADF4351,can it do that?If cannot, recommend some other PLL/CLOCK

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  • Hi,

    In my project,If I use HMC7044,it maybe work at single PLL2 mode,oscin is a LVPECL 10MHz refclk,because the phase between output 2560MHz and input 10MHz is stable(even at Multiple power-on ).

    like this,

    So,based on the above design,I just get a 163fs jitter.How to improve the jitter?

    I need your help.

    lichao

  • You can improve it by enabling the OSCIN doubler and using 20 MHz PFD2 frequency but this won't provide 100 fs jitter.

    You can connect your 10 MHz to PLL1 reference input and select a VCXO (which has a high GCD with your interested VCO frequency, just to ensure you have a high PFD frenquency) and connect it to OSCIN.

    By doing so, the VCXO that is connected to OSCIN will be locked on to 10 MHz via PLL1 and internal VCO will be locked on to VCXO. In this way, you will achieve a very good jitter performance.

    Kudret